Jon P. Santamauro

Array ( [id] => 3944581 [patent_doc_number] => 05872464 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-16 [patent_title] => 'Input buffer with stabilized trip points' [patent_app_type] => 1 [patent_app_number] => 8/696008 [patent_app_country] => US [patent_app_date] => 1996-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3006 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/872/05872464.pdf [firstpage_image] =>[orig_patent_app_number] => 696008 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3866983 [patent_doc_number] => 05793227 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'Synchronizing logic avoiding metastability' [patent_app_type] => 1 [patent_app_number] => 8/694048 [patent_app_country] => US [patent_app_date] => 1996-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 5052 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/793/05793227.pdf [firstpage_image] =>[orig_patent_app_number] => 694048 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3784547 [patent_doc_number] => 05818261 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Pseudo differential bus driver/receiver for field programmable devices' [patent_app_type] => 1 [patent_app_number] => 8/694891 [patent_app_country] => US [patent_app_date] => 1996-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3370 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/818/05818261.pdf [firstpage_image] =>[orig_patent_app_number] => 694891 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3974764 [patent_doc_number] => 05886541 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-23 [patent_title] => 'Combined logic gate and latch' [patent_app_type] => 1 [patent_app_number] => 8/692541 [patent_app_country] => US [patent_app_date] => 1996-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 3502 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/886/05886541.pdf [firstpage_image] =>[orig_patent_app_number] => 692541 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4192549 [patent_doc_number] => 06094066 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Tiered routing architecture for field programmable gate arrays' [patent_app_type] => 1 [patent_app_number] => 9/128986 [patent_app_country] => US [patent_app_date] => 1996-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 4577 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/094/06094066.pdf [firstpage_image] =>[orig_patent_app_number] => 128986 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3595454 [patent_doc_number] => 05585745 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-17 [patent_title] => 'Method and apparatus for reducing power consumption in digital electronic circuits' [patent_app_type] => 1 [patent_app_number] => 8/686272 [patent_app_country] => US [patent_app_date] => 1996-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5324 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/585/05585745.pdf [firstpage_image] =>[orig_patent_app_number] => 686272 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4104813 [patent_doc_number] => 06049223 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory' [patent_app_type] => 1 [patent_app_number] => 8/707705 [patent_app_country] => US [patent_app_date] => 1996-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 13118 [patent_no_of_claims] => 162 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/049/06049223.pdf [firstpage_image] =>[orig_patent_app_number] => 707705 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3752323 [patent_doc_number] => 05717343 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-10 [patent_title] => 'High-drive CMOS output buffer with noise supression using pulsed drivers and neighbor-sensing' [patent_app_type] => 1 [patent_app_number] => 8/685142 [patent_app_country] => US [patent_app_date] => 1996-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5712 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/717/05717343.pdf [firstpage_image] =>[orig_patent_app_number] => 685142 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3799040 [patent_doc_number] => 05726583 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-10 [patent_title] => 'Programmable dynamic line-termination circuit' [patent_app_type] => 1 [patent_app_number] => 8/690227 [patent_app_country] => US [patent_app_date] => 1996-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3742 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/726/05726583.pdf [firstpage_image] =>[orig_patent_app_number] => 690227 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3801320 [patent_doc_number] => 05781034 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'Reduced output swing with p-channel pullup diode connected' [patent_app_type] => 1 [patent_app_number] => 8/680288 [patent_app_country] => US [patent_app_date] => 1996-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4402 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/781/05781034.pdf [firstpage_image] =>[orig_patent_app_number] => 680288 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4055783 [patent_doc_number] => 05869984 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-09 [patent_title] => 'Output buffer circuit utilizing FETS for lowering output resistance of a circuit block' [patent_app_type] => 1 [patent_app_number] => 8/673475 [patent_app_country] => US [patent_app_date] => 1996-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 7142 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 360 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/869/05869984.pdf [firstpage_image] =>[orig_patent_app_number] => 673475 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3822962 [patent_doc_number] => 05789944 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-04 [patent_title] => 'Asynchronous anticontention logic for bi-directional signals' [patent_app_type] => 1 [patent_app_number] => 8/672723 [patent_app_country] => US [patent_app_date] => 1996-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9166 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/789/05789944.pdf [firstpage_image] =>[orig_patent_app_number] => 672723 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3859633 [patent_doc_number] => 05767701 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Synchronous contention prevention logic for bi-directional signals' [patent_app_type] => 1 [patent_app_number] => 8/672730 [patent_app_country] => US [patent_app_date] => 1996-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8499 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/767/05767701.pdf [firstpage_image] =>[orig_patent_app_number] => 672730 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4050203 [patent_doc_number] => 05909126 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-01 [patent_title] => 'Programmable logic array integrated circuit devices with interleaved logic array blocks' [patent_app_type] => 1 [patent_app_number] => 8/672676 [patent_app_country] => US [patent_app_date] => 1996-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6015 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/909/05909126.pdf [firstpage_image] =>[orig_patent_app_number] => 672676 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3910786 [patent_doc_number] => 05898316 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Mode setting circuit of semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/673244 [patent_app_country] => US [patent_app_date] => 1996-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 5991 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/898/05898316.pdf [firstpage_image] =>[orig_patent_app_number] => 673244 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3859619 [patent_doc_number] => 05767700 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Pulse signal transfer unit employing post charge logic' [patent_app_type] => 1 [patent_app_number] => 8/673210 [patent_app_country] => US [patent_app_date] => 1996-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 3008 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/767/05767700.pdf [firstpage_image] =>[orig_patent_app_number] => 673210 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3736692 [patent_doc_number] => 05635861 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-03 [patent_title] => 'Off chip driver circuit' [patent_app_type] => 1 [patent_app_number] => 8/671045 [patent_app_country] => US [patent_app_date] => 1996-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3744 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/635/05635861.pdf [firstpage_image] =>[orig_patent_app_number] => 671045 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4226179 [patent_doc_number] => 06040711 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'CMOS output buffer having a switchable bulk line' [patent_app_type] => 1 [patent_app_number] => 8/670000 [patent_app_country] => US [patent_app_date] => 1996-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3540 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/040/06040711.pdf [firstpage_image] =>[orig_patent_app_number] => 670000 [rel_patent_id] =>[rel_patent_doc_number] =>)