Search

Jon P. Santamauro

Examiner (ID: 474)

Most Active Art Unit
2819
Art Unit(s)
2819, 2509, 2878
Total Applications
622
Issued Applications
539
Pending Applications
28
Abandoned Applications
55

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3933990 [patent_doc_number] => 05952847 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Multiple logic family compatible output driver' [patent_app_type] => 1 [patent_app_number] => 8/673701 [patent_app_country] => US [patent_app_date] => 1996-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 8072 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/952/05952847.pdf [firstpage_image] =>[orig_patent_app_number] => 673701 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/673701
Multiple logic family compatible output driver Jun 24, 1996 Issued
Array ( [id] => 3847185 [patent_doc_number] => 05847575 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-08 [patent_title] => 'Method and apparatus for performing switched supply drive in CMOS pad drivers' [patent_app_type] => 1 [patent_app_number] => 8/668170 [patent_app_country] => US [patent_app_date] => 1996-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4213 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/847/05847575.pdf [firstpage_image] =>[orig_patent_app_number] => 668170 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/668170
Method and apparatus for performing switched supply drive in CMOS pad drivers Jun 20, 1996 Issued
Array ( [id] => 3801227 [patent_doc_number] => 05781028 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'System and method for a switched data bus termination' [patent_app_type] => 1 [patent_app_number] => 8/668287 [patent_app_country] => US [patent_app_date] => 1996-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 7202 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 19 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/781/05781028.pdf [firstpage_image] =>[orig_patent_app_number] => 668287 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/668287
System and method for a switched data bus termination Jun 20, 1996 Issued
Array ( [id] => 3747345 [patent_doc_number] => 05786711 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-28 [patent_title] => 'Data output buffer for use in a semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/668094 [patent_app_country] => US [patent_app_date] => 1996-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2786 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/786/05786711.pdf [firstpage_image] =>[orig_patent_app_number] => 668094 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/668094
Data output buffer for use in a semiconductor memory device Jun 16, 1996 Issued
Array ( [id] => 4042581 [patent_doc_number] => 05856746 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-05 [patent_title] => 'Logic speed-up by selecting true/false combinations with the slowest logic signal' [patent_app_type] => 1 [patent_app_number] => 8/664567 [patent_app_country] => US [patent_app_date] => 1996-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2269 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/856/05856746.pdf [firstpage_image] =>[orig_patent_app_number] => 664567 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/664567
Logic speed-up by selecting true/false combinations with the slowest logic signal Jun 16, 1996 Issued
Array ( [id] => 3768642 [patent_doc_number] => 05844426 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Read Channel device' [patent_app_type] => 1 [patent_app_number] => 8/665144 [patent_app_country] => US [patent_app_date] => 1996-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 65 [patent_figures_cnt] => 70 [patent_no_of_words] => 3200 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/844/05844426.pdf [firstpage_image] =>[orig_patent_app_number] => 665144 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/665144
Read Channel device Jun 12, 1996 Issued
Array ( [id] => 3707524 [patent_doc_number] => 05646551 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-08 [patent_title] => 'Mixed mode output buffer circuit for CMOSIC' [patent_app_type] => 1 [patent_app_number] => 8/663440 [patent_app_country] => US [patent_app_date] => 1996-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3874 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 340 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/646/05646551.pdf [firstpage_image] =>[orig_patent_app_number] => 663440 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/663440
Mixed mode output buffer circuit for CMOSIC Jun 12, 1996 Issued
Array ( [id] => 3688038 [patent_doc_number] => 05633604 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-27 [patent_title] => 'Mixed mode output buffer circuit for CMOSIC' [patent_app_type] => 1 [patent_app_number] => 8/663437 [patent_app_country] => US [patent_app_date] => 1996-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3874 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 328 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/633/05633604.pdf [firstpage_image] =>[orig_patent_app_number] => 663437 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/663437
Mixed mode output buffer circuit for CMOSIC Jun 12, 1996 Issued
Array ( [id] => 3784462 [patent_doc_number] => 05818256 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Low power combinational logic circuit' [patent_app_type] => 1 [patent_app_number] => 8/661764 [patent_app_country] => US [patent_app_date] => 1996-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4530 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/818/05818256.pdf [firstpage_image] =>[orig_patent_app_number] => 661764 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/661764
Low power combinational logic circuit Jun 10, 1996 Issued
Array ( [id] => 4019435 [patent_doc_number] => 05963056 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Full and empty flag generator for synchronous FIFOs' [patent_app_type] => 1 [patent_app_number] => 8/661436 [patent_app_country] => US [patent_app_date] => 1996-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3910 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/963/05963056.pdf [firstpage_image] =>[orig_patent_app_number] => 661436 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/661436
Full and empty flag generator for synchronous FIFOs Jun 10, 1996 Issued
Array ( [id] => 3894318 [patent_doc_number] => 05777491 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-07 [patent_title] => 'High-performance differential cascode voltage switch with pass gate logic elements' [patent_app_type] => 1 [patent_app_number] => 8/660836 [patent_app_country] => US [patent_app_date] => 1996-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 4898 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 495 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/777/05777491.pdf [firstpage_image] =>[orig_patent_app_number] => 660836 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/660836
High-performance differential cascode voltage switch with pass gate logic elements Jun 9, 1996 Issued
Array ( [id] => 3905669 [patent_doc_number] => 05751162 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'Field programmable gate array logic module configurable as combinational or sequential circuits' [patent_app_type] => 1 [patent_app_number] => 8/659990 [patent_app_country] => US [patent_app_date] => 1996-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 30 [patent_no_of_words] => 6438 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/751/05751162.pdf [firstpage_image] =>[orig_patent_app_number] => 659990 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/659990
Field programmable gate array logic module configurable as combinational or sequential circuits Jun 6, 1996 Issued
Array ( [id] => 3859653 [patent_doc_number] => 05767702 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Switched pull down emitter coupled logic circuits' [patent_app_type] => 1 [patent_app_number] => 8/660237 [patent_app_country] => US [patent_app_date] => 1996-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 27 [patent_no_of_words] => 12977 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/767/05767702.pdf [firstpage_image] =>[orig_patent_app_number] => 660237 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/660237
Switched pull down emitter coupled logic circuits Jun 6, 1996 Issued
08/658610 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE Jun 4, 1996 Abandoned
Array ( [id] => 3905726 [patent_doc_number] => 05751166 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'Input buffer circuit and method' [patent_app_type] => 1 [patent_app_number] => 8/658040 [patent_app_country] => US [patent_app_date] => 1996-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3976 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/751/05751166.pdf [firstpage_image] =>[orig_patent_app_number] => 658040 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/658040
Input buffer circuit and method Jun 3, 1996 Issued
Array ( [id] => 3799146 [patent_doc_number] => 05726590 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-10 [patent_title] => 'Interface in a semiconductor integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/660174 [patent_app_country] => US [patent_app_date] => 1996-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3335 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/726/05726590.pdf [firstpage_image] =>[orig_patent_app_number] => 660174 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/660174
Interface in a semiconductor integrated circuit Jun 2, 1996 Issued
Array ( [id] => 3847492 [patent_doc_number] => 05744979 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-28 [patent_title] => 'FPGA having logic cells configured by SRAM memory cells and interconnect configured by antifuses' [patent_app_type] => 1 [patent_app_number] => 8/656753 [patent_app_country] => US [patent_app_date] => 1996-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 71 [patent_no_of_words] => 13248 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/744/05744979.pdf [firstpage_image] =>[orig_patent_app_number] => 656753 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/656753
FPGA having logic cells configured by SRAM memory cells and interconnect configured by antifuses Jun 2, 1996 Issued
Array ( [id] => 4021334 [patent_doc_number] => 05880603 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'MOS output buffer with overvoltage protection circuitry' [patent_app_type] => 1 [patent_app_number] => 8/657599 [patent_app_country] => US [patent_app_date] => 1996-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 30 [patent_no_of_words] => 14757 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/880/05880603.pdf [firstpage_image] =>[orig_patent_app_number] => 657599 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/657599
MOS output buffer with overvoltage protection circuitry May 30, 1996 Issued
Array ( [id] => 3803839 [patent_doc_number] => 05828237 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Emitter coupled logic (ECL) gate and method of forming same' [patent_app_type] => 1 [patent_app_number] => 8/656543 [patent_app_country] => US [patent_app_date] => 1996-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2184 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/828/05828237.pdf [firstpage_image] =>[orig_patent_app_number] => 656543 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/656543
Emitter coupled logic (ECL) gate and method of forming same May 30, 1996 Issued
Array ( [id] => 3974751 [patent_doc_number] => 05886540 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-23 [patent_title] => 'Evaluation phase expansion for dynamic logic circuits' [patent_app_type] => 1 [patent_app_number] => 8/658920 [patent_app_country] => US [patent_app_date] => 1996-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 7772 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/886/05886540.pdf [firstpage_image] =>[orig_patent_app_number] => 658920 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/658920
Evaluation phase expansion for dynamic logic circuits May 30, 1996 Issued
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