
Jon P. Santamauro
Examiner (ID: 474)
| Most Active Art Unit | 2819 |
| Art Unit(s) | 2819, 2509, 2878 |
| Total Applications | 622 |
| Issued Applications | 539 |
| Pending Applications | 28 |
| Abandoned Applications | 55 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3782235
[patent_doc_number] => 05808477
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-15
[patent_title] => 'Circuit for detection and protection against short circuits for digital outputs'
[patent_app_type] => 1
[patent_app_number] => 8/657878
[patent_app_country] => US
[patent_app_date] => 1996-05-31
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[patent_no_of_words] => 2683
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[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/808/05808477.pdf
[firstpage_image] =>[orig_patent_app_number] => 657878
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/657878 | Circuit for detection and protection against short circuits for digital outputs | May 30, 1996 | Issued |
Array
(
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[patent_doc_number] => 05867036
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-02
[patent_title] => 'Domino scan architecture and domino scan flip-flop for the testing of domino and hybrid CMOS circuits'
[patent_app_type] => 1
[patent_app_number] => 8/655438
[patent_app_country] => US
[patent_app_date] => 1996-05-29
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/655438 | Domino scan architecture and domino scan flip-flop for the testing of domino and hybrid CMOS circuits | May 28, 1996 | Issued |
Array
(
[id] => 3859609
[patent_doc_number] => 05767699
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[patent_kind] => NA
[patent_issue_date] => 1998-06-16
[patent_title] => 'Fully complementary differential output driver for high speed digital communications'
[patent_app_type] => 1
[patent_app_number] => 8/653788
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[patent_app_date] => 1996-05-28
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[firstpage_image] =>[orig_patent_app_number] => 653788
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/653788 | Fully complementary differential output driver for high speed digital communications | May 27, 1996 | Issued |
Array
(
[id] => 4069083
[patent_doc_number] => 05896041
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[patent_issue_date] => 1999-04-20
[patent_title] => 'Method and apparatus for programming anti-fuses using internally generated programming voltage'
[patent_app_type] => 1
[patent_app_number] => 8/654338
[patent_app_country] => US
[patent_app_date] => 1996-05-28
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[firstpage_image] =>[orig_patent_app_number] => 654338
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/654338 | Method and apparatus for programming anti-fuses using internally generated programming voltage | May 27, 1996 | Issued |
Array
(
[id] => 3803816
[patent_doc_number] => 05828235
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-27
[patent_title] => 'Semiconductor integrated circuit device having power reduction mechanism'
[patent_app_type] => 1
[patent_app_number] => 8/653248
[patent_app_country] => US
[patent_app_date] => 1996-05-24
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[firstpage_image] =>[orig_patent_app_number] => 653248
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/653248 | Semiconductor integrated circuit device having power reduction mechanism | May 23, 1996 | Issued |
Array
(
[id] => 4103951
[patent_doc_number] => RE036952
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-14
[patent_title] => 'One time programmable fully-testable programmable logic device with zero power and anti-fuse cell architecture'
[patent_app_type] => 2
[patent_app_number] => 8/653516
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/653516 | One time programmable fully-testable programmable logic device with zero power and anti-fuse cell architecture | May 23, 1996 | Issued |
Array
(
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[patent_doc_number] => 05602496
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[patent_issue_date] => 1997-02-11
[patent_title] => 'Input buffer circuit including an input level translator with sleep function'
[patent_app_type] => 1
[patent_app_number] => 8/652888
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/652888 | Input buffer circuit including an input level translator with sleep function | May 22, 1996 | Issued |
Array
(
[id] => 3893149
[patent_doc_number] => 05714891
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-03
[patent_title] => 'Multiple-valued literal circuit using resonant tunneling diodes'
[patent_app_type] => 1
[patent_app_number] => 8/650178
[patent_app_country] => US
[patent_app_date] => 1996-05-20
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/714/05714891.pdf
[firstpage_image] =>[orig_patent_app_number] => 650178
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/650178 | Multiple-valued literal circuit using resonant tunneling diodes | May 19, 1996 | Issued |
Array
(
[id] => 3882262
[patent_doc_number] => 05825208
[patent_country] => US
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[patent_issue_date] => 1998-10-20
[patent_title] => 'Method and apparatus for fast evaluation of dynamic CMOS logic circuits'
[patent_app_type] => 1
[patent_app_number] => 8/650691
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[patent_app_date] => 1996-05-20
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[firstpage_image] =>[orig_patent_app_number] => 650691
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/650691 | Method and apparatus for fast evaluation of dynamic CMOS logic circuits | May 19, 1996 | Issued |
Array
(
[id] => 3910772
[patent_doc_number] => 05898315
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[patent_issue_date] => 1999-04-27
[patent_title] => 'Output buffer circuit and method having improved access'
[patent_app_type] => 1
[patent_app_number] => 8/649302
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[pdf_file] => patents/05/898/05898315.pdf
[firstpage_image] =>[orig_patent_app_number] => 649302
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/649302 | Output buffer circuit and method having improved access | May 16, 1996 | Issued |
Array
(
[id] => 4071584
[patent_doc_number] => 05867039
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[patent_kind] => NA
[patent_issue_date] => 1999-02-02
[patent_title] => 'CMOS output driver with p-channel substrate tracking for cold spare capability'
[patent_app_type] => 1
[patent_app_number] => 8/649344
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[patent_app_date] => 1996-05-17
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/649344 | CMOS output driver with p-channel substrate tracking for cold spare capability | May 16, 1996 | Issued |
Array
(
[id] => 3792409
[patent_doc_number] => 05736869
[patent_country] => US
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[patent_issue_date] => 1998-04-07
[patent_title] => 'Output driver with level shifting and voltage protection'
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[patent_app_number] => 8/645644
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[firstpage_image] =>[orig_patent_app_number] => 645644
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/645644 | Output driver with level shifting and voltage protection | May 15, 1996 | Issued |
Array
(
[id] => 3734395
[patent_doc_number] => 05703500
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[patent_title] => 'Threshold voltage scalable buffer with reference level'
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[firstpage_image] =>[orig_patent_app_number] => 648443
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/648443 | Threshold voltage scalable buffer with reference level | May 14, 1996 | Issued |
Array
(
[id] => 3848482
[patent_doc_number] => 05708374
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[patent_issue_date] => 1998-01-13
[patent_title] => 'Self-timed control circuit for self-resetting logic circuitry'
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[patent_app_number] => 8/647492
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[firstpage_image] =>[orig_patent_app_number] => 647492
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/647492 | Self-timed control circuit for self-resetting logic circuitry | May 13, 1996 | Issued |
Array
(
[id] => 4021408
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[patent_issue_date] => 1999-03-09
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Array
(
[id] => 3782482
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[patent_issue_date] => 1998-05-26
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Array
(
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Array
(
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Array
(
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Array
(
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[pdf_file] => patents/05/680/05680063.pdf
[firstpage_image] =>[orig_patent_app_number] => 636358
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/636358 | Bi-directional voltage translator | Apr 22, 1996 | Issued |