Search

Jon P. Santamauro

Examiner (ID: 474)

Most Active Art Unit
2819
Art Unit(s)
2819, 2509, 2878
Total Applications
622
Issued Applications
539
Pending Applications
28
Abandoned Applications
55

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3782235 [patent_doc_number] => 05808477 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'Circuit for detection and protection against short circuits for digital outputs' [patent_app_type] => 1 [patent_app_number] => 8/657878 [patent_app_country] => US [patent_app_date] => 1996-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2683 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/808/05808477.pdf [firstpage_image] =>[orig_patent_app_number] => 657878 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/657878
Circuit for detection and protection against short circuits for digital outputs May 30, 1996 Issued
Array ( [id] => 4071539 [patent_doc_number] => 05867036 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'Domino scan architecture and domino scan flip-flop for the testing of domino and hybrid CMOS circuits' [patent_app_type] => 1 [patent_app_number] => 8/655438 [patent_app_country] => US [patent_app_date] => 1996-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 6197 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/867/05867036.pdf [firstpage_image] =>[orig_patent_app_number] => 655438 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/655438
Domino scan architecture and domino scan flip-flop for the testing of domino and hybrid CMOS circuits May 28, 1996 Issued
Array ( [id] => 3859609 [patent_doc_number] => 05767699 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Fully complementary differential output driver for high speed digital communications' [patent_app_type] => 1 [patent_app_number] => 8/653788 [patent_app_country] => US [patent_app_date] => 1996-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3240 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/767/05767699.pdf [firstpage_image] =>[orig_patent_app_number] => 653788 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/653788
Fully complementary differential output driver for high speed digital communications May 27, 1996 Issued
Array ( [id] => 4069083 [patent_doc_number] => 05896041 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Method and apparatus for programming anti-fuses using internally generated programming voltage' [patent_app_type] => 1 [patent_app_number] => 8/654338 [patent_app_country] => US [patent_app_date] => 1996-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 12 [patent_no_of_words] => 3818 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/896/05896041.pdf [firstpage_image] =>[orig_patent_app_number] => 654338 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/654338
Method and apparatus for programming anti-fuses using internally generated programming voltage May 27, 1996 Issued
Array ( [id] => 3803816 [patent_doc_number] => 05828235 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Semiconductor integrated circuit device having power reduction mechanism' [patent_app_type] => 1 [patent_app_number] => 8/653248 [patent_app_country] => US [patent_app_date] => 1996-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 59 [patent_no_of_words] => 18594 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/828/05828235.pdf [firstpage_image] =>[orig_patent_app_number] => 653248 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/653248
Semiconductor integrated circuit device having power reduction mechanism May 23, 1996 Issued
Array ( [id] => 4103951 [patent_doc_number] => RE036952 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'One time programmable fully-testable programmable logic device with zero power and anti-fuse cell architecture' [patent_app_type] => 2 [patent_app_number] => 8/653516 [patent_app_country] => US [patent_app_date] => 1996-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2596 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 37 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/036/RE036952.pdf [firstpage_image] =>[orig_patent_app_number] => 653516 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/653516
One time programmable fully-testable programmable logic device with zero power and anti-fuse cell architecture May 23, 1996 Issued
Array ( [id] => 3629076 [patent_doc_number] => 05602496 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-11 [patent_title] => 'Input buffer circuit including an input level translator with sleep function' [patent_app_type] => 1 [patent_app_number] => 8/652888 [patent_app_country] => US [patent_app_date] => 1996-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4958 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/602/05602496.pdf [firstpage_image] =>[orig_patent_app_number] => 652888 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/652888
Input buffer circuit including an input level translator with sleep function May 22, 1996 Issued
Array ( [id] => 3893149 [patent_doc_number] => 05714891 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-03 [patent_title] => 'Multiple-valued literal circuit using resonant tunneling diodes' [patent_app_type] => 1 [patent_app_number] => 8/650178 [patent_app_country] => US [patent_app_date] => 1996-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 3128 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/714/05714891.pdf [firstpage_image] =>[orig_patent_app_number] => 650178 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/650178
Multiple-valued literal circuit using resonant tunneling diodes May 19, 1996 Issued
Array ( [id] => 3882262 [patent_doc_number] => 05825208 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-20 [patent_title] => 'Method and apparatus for fast evaluation of dynamic CMOS logic circuits' [patent_app_type] => 1 [patent_app_number] => 8/650691 [patent_app_country] => US [patent_app_date] => 1996-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4256 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/825/05825208.pdf [firstpage_image] =>[orig_patent_app_number] => 650691 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/650691
Method and apparatus for fast evaluation of dynamic CMOS logic circuits May 19, 1996 Issued
Array ( [id] => 3910772 [patent_doc_number] => 05898315 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Output buffer circuit and method having improved access' [patent_app_type] => 1 [patent_app_number] => 8/649302 [patent_app_country] => US [patent_app_date] => 1996-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4363 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/898/05898315.pdf [firstpage_image] =>[orig_patent_app_number] => 649302 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/649302
Output buffer circuit and method having improved access May 16, 1996 Issued
Array ( [id] => 4071584 [patent_doc_number] => 05867039 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'CMOS output driver with p-channel substrate tracking for cold spare capability' [patent_app_type] => 1 [patent_app_number] => 8/649344 [patent_app_country] => US [patent_app_date] => 1996-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2950 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/867/05867039.pdf [firstpage_image] =>[orig_patent_app_number] => 649344 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/649344
CMOS output driver with p-channel substrate tracking for cold spare capability May 16, 1996 Issued
Array ( [id] => 3792409 [patent_doc_number] => 05736869 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-07 [patent_title] => 'Output driver with level shifting and voltage protection' [patent_app_type] => 1 [patent_app_number] => 8/645644 [patent_app_country] => US [patent_app_date] => 1996-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5229 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/736/05736869.pdf [firstpage_image] =>[orig_patent_app_number] => 645644 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/645644
Output driver with level shifting and voltage protection May 15, 1996 Issued
Array ( [id] => 3734395 [patent_doc_number] => 05703500 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-30 [patent_title] => 'Threshold voltage scalable buffer with reference level' [patent_app_type] => 1 [patent_app_number] => 8/648443 [patent_app_country] => US [patent_app_date] => 1996-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4311 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/703/05703500.pdf [firstpage_image] =>[orig_patent_app_number] => 648443 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/648443
Threshold voltage scalable buffer with reference level May 14, 1996 Issued
Array ( [id] => 3848482 [patent_doc_number] => 05708374 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-13 [patent_title] => 'Self-timed control circuit for self-resetting logic circuitry' [patent_app_type] => 1 [patent_app_number] => 8/647492 [patent_app_country] => US [patent_app_date] => 1996-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4203 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/708/05708374.pdf [firstpage_image] =>[orig_patent_app_number] => 647492 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/647492
Self-timed control circuit for self-resetting logic circuitry May 13, 1996 Issued
Array ( [id] => 4021408 [patent_doc_number] => 05880607 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'Clock distribution network with modular buffers' [patent_app_type] => 1 [patent_app_number] => 8/640721 [patent_app_country] => US [patent_app_date] => 1996-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4292 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/880/05880607.pdf [firstpage_image] =>[orig_patent_app_number] => 640721 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/640721
Clock distribution network with modular buffers Apr 30, 1996 Issued
Array ( [id] => 3782482 [patent_doc_number] => 05757208 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-26 [patent_title] => 'Programmable array and method for routing power busses therein' [patent_app_type] => 1 [patent_app_number] => 8/641397 [patent_app_country] => US [patent_app_date] => 1996-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 4037 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/757/05757208.pdf [firstpage_image] =>[orig_patent_app_number] => 641397 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/641397
Programmable array and method for routing power busses therein Apr 30, 1996 Issued
Array ( [id] => 3791076 [patent_doc_number] => 05821770 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'Option decoding with on-chip electrical fuses' [patent_app_type] => 1 [patent_app_number] => 8/640032 [patent_app_country] => US [patent_app_date] => 1996-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3580 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/821/05821770.pdf [firstpage_image] =>[orig_patent_app_number] => 640032 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/640032
Option decoding with on-chip electrical fuses Apr 29, 1996 Issued
Array ( [id] => 3694219 [patent_doc_number] => 05663663 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-02 [patent_title] => 'Mixed voltage interface converter' [patent_app_type] => 1 [patent_app_number] => 8/638028 [patent_app_country] => US [patent_app_date] => 1996-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1716 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/663/05663663.pdf [firstpage_image] =>[orig_patent_app_number] => 638028 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/638028
Mixed voltage interface converter Apr 25, 1996 Issued
Array ( [id] => 3784525 [patent_doc_number] => 05818260 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Transmission line driver having controllable rise and fall times with variable output low and minimal on/off delay' [patent_app_type] => 1 [patent_app_number] => 8/639921 [patent_app_country] => US [patent_app_date] => 1996-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 10738 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/818/05818260.pdf [firstpage_image] =>[orig_patent_app_number] => 639921 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/639921
Transmission line driver having controllable rise and fall times with variable output low and minimal on/off delay Apr 23, 1996 Issued
Array ( [id] => 3699923 [patent_doc_number] => 05680063 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-21 [patent_title] => 'Bi-directional voltage translator' [patent_app_type] => 1 [patent_app_number] => 8/636358 [patent_app_country] => US [patent_app_date] => 1996-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4417 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/680/05680063.pdf [firstpage_image] =>[orig_patent_app_number] => 636358 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/636358
Bi-directional voltage translator Apr 22, 1996 Issued
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