
Jon P. Santamauro
Examiner (ID: 474)
| Most Active Art Unit | 2819 |
| Art Unit(s) | 2819, 2509, 2878 |
| Total Applications | 622 |
| Issued Applications | 539 |
| Pending Applications | 28 |
| Abandoned Applications | 55 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3884554
[patent_doc_number] => 05804987
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-08
[patent_title] => 'LSI chip having programmable buffer circuit'
[patent_app_type] => 1
[patent_app_number] => 8/636131
[patent_app_country] => US
[patent_app_date] => 1996-04-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 22
[patent_no_of_words] => 5047
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 217
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/804/05804987.pdf
[firstpage_image] =>[orig_patent_app_number] => 636131
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/636131 | LSI chip having programmable buffer circuit | Apr 21, 1996 | Issued |
| 08/635853 | RADIATION RESISTANT LOGIC CIRCUIT | Apr 21, 1996 | Abandoned |
Array
(
[id] => 3791065
[patent_doc_number] => 05821769
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-13
[patent_title] => 'Low voltage CMOS logic circuit with threshold voltage control'
[patent_app_type] => 1
[patent_app_number] => 8/634552
[patent_app_country] => US
[patent_app_date] => 1996-04-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 47
[patent_no_of_words] => 10323
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/821/05821769.pdf
[firstpage_image] =>[orig_patent_app_number] => 634552
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/634552 | Low voltage CMOS logic circuit with threshold voltage control | Apr 17, 1996 | Issued |
Array
(
[id] => 3905683
[patent_doc_number] => 05751163
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-12
[patent_title] => 'Parallel programming of in-system (ISP) programmable devices using an automatic tester'
[patent_app_type] => 1
[patent_app_number] => 8/632811
[patent_app_country] => US
[patent_app_date] => 1996-04-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 17
[patent_no_of_words] => 4991
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 288
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/751/05751163.pdf
[firstpage_image] =>[orig_patent_app_number] => 632811
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/632811 | Parallel programming of in-system (ISP) programmable devices using an automatic tester | Apr 15, 1996 | Issued |
Array
(
[id] => 4004581
[patent_doc_number] => 05923189
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-13
[patent_title] => 'Semiconductor integrated circuit comprised of pass-transistor circuits with different mutual connections'
[patent_app_type] => 1
[patent_app_number] => 8/633053
[patent_app_country] => US
[patent_app_date] => 1996-04-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4524
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 379
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/923/05923189.pdf
[firstpage_image] =>[orig_patent_app_number] => 633053
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/633053 | Semiconductor integrated circuit comprised of pass-transistor circuits with different mutual connections | Apr 15, 1996 | Issued |
Array
(
[id] => 3669883
[patent_doc_number] => 05598109
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-01-28
[patent_title] => 'Programmable logic array device with grouped logic regions and three types of conductors'
[patent_app_type] => 1
[patent_app_number] => 8/626513
[patent_app_country] => US
[patent_app_date] => 1996-04-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 7575
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 321
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/598/05598109.pdf
[firstpage_image] =>[orig_patent_app_number] => 626513
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/626513 | Programmable logic array device with grouped logic regions and three types of conductors | Apr 1, 1996 | Issued |
Array
(
[id] => 3884587
[patent_doc_number] => 05804989
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-08
[patent_title] => 'Logic circuit for a semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 8/627343
[patent_app_country] => US
[patent_app_date] => 1996-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 2662
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 191
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/804/05804989.pdf
[firstpage_image] =>[orig_patent_app_number] => 627343
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/627343 | Logic circuit for a semiconductor memory device | Mar 31, 1996 | Issued |
Array
(
[id] => 3982425
[patent_doc_number] => 05917342
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-29
[patent_title] => 'BiMOS integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 8/623834
[patent_app_country] => US
[patent_app_date] => 1996-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 12
[patent_no_of_words] => 4350
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/917/05917342.pdf
[firstpage_image] =>[orig_patent_app_number] => 623834
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/623834 | BiMOS integrated circuit | Mar 28, 1996 | Issued |
Array
(
[id] => 3837659
[patent_doc_number] => 05739701
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-14
[patent_title] => 'Input/output buffer circuit having reduced power consumption'
[patent_app_type] => 1
[patent_app_number] => 8/623002
[patent_app_country] => US
[patent_app_date] => 1996-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 22
[patent_no_of_words] => 8054
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 250
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/739/05739701.pdf
[firstpage_image] =>[orig_patent_app_number] => 623002
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/623002 | Input/output buffer circuit having reduced power consumption | Mar 27, 1996 | Issued |
Array
(
[id] => 3734336
[patent_doc_number] => 05703496
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-30
[patent_title] => 'Method and apparatus for limiting the slew rate of output drivers by selectively programming the threshold voltage of flash cells connected thereto'
[patent_app_type] => 1
[patent_app_number] => 8/623412
[patent_app_country] => US
[patent_app_date] => 1996-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 6414
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/703/05703496.pdf
[firstpage_image] =>[orig_patent_app_number] => 623412
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/623412 | Method and apparatus for limiting the slew rate of output drivers by selectively programming the threshold voltage of flash cells connected thereto | Mar 27, 1996 | Issued |
Array
(
[id] => 3742595
[patent_doc_number] => 05698993
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-16
[patent_title] => 'CMOS level shifting circuit'
[patent_app_type] => 1
[patent_app_number] => 8/623351
[patent_app_country] => US
[patent_app_date] => 1996-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 7612
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 297
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/698/05698993.pdf
[firstpage_image] =>[orig_patent_app_number] => 623351
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/623351 | CMOS level shifting circuit | Mar 27, 1996 | Issued |
| 08/622124 | LOW OVERHEAD MEMORY DESIGNS FOR IC TERMINALS | Mar 25, 1996 | Abandoned |
Array
(
[id] => 3817804
[patent_doc_number] => 05811990
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-22
[patent_title] => 'Voltage pump and a level translator circuit'
[patent_app_type] => 1
[patent_app_number] => 8/616026
[patent_app_country] => US
[patent_app_date] => 1996-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
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[patent_no_of_words] => 8555
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/811/05811990.pdf
[firstpage_image] =>[orig_patent_app_number] => 616026
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/616026 | Voltage pump and a level translator circuit | Mar 12, 1996 | Issued |
Array
(
[id] => 3881430
[patent_doc_number] => 05764079
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-09
[patent_title] => 'Sample and load scheme for observability of internal nodes in a PLD'
[patent_app_type] => 1
[patent_app_number] => 8/615342
[patent_app_country] => US
[patent_app_date] => 1996-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/764/05764079.pdf
[firstpage_image] =>[orig_patent_app_number] => 615342
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/615342 | Sample and load scheme for observability of internal nodes in a PLD | Mar 10, 1996 | Issued |
Array
(
[id] => 3775515
[patent_doc_number] => 05734272
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-31
[patent_title] => 'Differential stage logic circuit'
[patent_app_type] => 1
[patent_app_number] => 8/611426
[patent_app_country] => US
[patent_app_date] => 1996-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/734/05734272.pdf
[firstpage_image] =>[orig_patent_app_number] => 611426
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/611426 | Differential stage logic circuit | Mar 5, 1996 | Issued |
Array
(
[id] => 3836943
[patent_doc_number] => 05760610
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-02
[patent_title] => 'Qualified universal clock buffer circuit for generating high gain, low skew local clock signals'
[patent_app_type] => 1
[patent_app_number] => 8/609306
[patent_app_country] => US
[patent_app_date] => 1996-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 6774
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[patent_no_of_ind_claims] => 3
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/760/05760610.pdf
[firstpage_image] =>[orig_patent_app_number] => 609306
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/609306 | Qualified universal clock buffer circuit for generating high gain, low skew local clock signals | Feb 29, 1996 | Issued |
Array
(
[id] => 3782275
[patent_doc_number] => 05808480
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-15
[patent_title] => 'High voltage swing output buffer in low voltage technology'
[patent_app_type] => 1
[patent_app_number] => 8/607954
[patent_app_country] => US
[patent_app_date] => 1996-02-29
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/808/05808480.pdf
[firstpage_image] =>[orig_patent_app_number] => 607954
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/607954 | High voltage swing output buffer in low voltage technology | Feb 28, 1996 | Issued |
Array
(
[id] => 3693278
[patent_doc_number] => 05696456
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-09
[patent_title] => 'Enhanced low voltage TTL interface'
[patent_app_type] => 1
[patent_app_number] => 8/600638
[patent_app_country] => US
[patent_app_date] => 1996-02-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[pdf_file] => patents/05/696/05696456.pdf
[firstpage_image] =>[orig_patent_app_number] => 600638
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/600638 | Enhanced low voltage TTL interface | Feb 28, 1996 | Issued |
Array
(
[id] => 4021321
[patent_doc_number] => 05880602
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-09
[patent_title] => 'Input and output buffer circuit'
[patent_app_type] => 1
[patent_app_number] => 8/608566
[patent_app_country] => US
[patent_app_date] => 1996-02-28
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/880/05880602.pdf
[firstpage_image] =>[orig_patent_app_number] => 608566
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/608566 | Input and output buffer circuit | Feb 27, 1996 | Issued |
Array
(
[id] => 3742547
[patent_doc_number] => 05698991
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-16
[patent_title] => 'Bus driver'
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[patent_app_number] => 8/607464
[patent_app_country] => US
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[pdf_file] => patents/05/698/05698991.pdf
[firstpage_image] =>[orig_patent_app_number] => 607464
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/607464 | Bus driver | Feb 26, 1996 | Issued |