
Jon P. Santamauro
Examiner (ID: 474)
| Most Active Art Unit | 2819 |
| Art Unit(s) | 2819, 2509, 2878 |
| Total Applications | 622 |
| Issued Applications | 539 |
| Pending Applications | 28 |
| Abandoned Applications | 55 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3867519
[patent_doc_number] => 05796267
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-18
[patent_title] => 'Tri-Statable input/output circuitry for programmable logic'
[patent_app_type] => 1
[patent_app_number] => 8/607849
[patent_app_country] => US
[patent_app_date] => 1996-02-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2720
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 392
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/796/05796267.pdf
[firstpage_image] =>[orig_patent_app_number] => 607849
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/607849 | Tri-Statable input/output circuitry for programmable logic | Feb 26, 1996 | Issued |
Array
(
[id] => 3792436
[patent_doc_number] => 05736871
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-07
[patent_title] => 'Differential pair input buffer circuit with a variable current source'
[patent_app_type] => 1
[patent_app_number] => 8/607574
[patent_app_country] => US
[patent_app_date] => 1996-02-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 3955
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[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 132
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/736/05736871.pdf
[firstpage_image] =>[orig_patent_app_number] => 607574
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/607574 | Differential pair input buffer circuit with a variable current source | Feb 26, 1996 | Issued |
Array
(
[id] => 3752336
[patent_doc_number] => 05717344
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-10
[patent_title] => 'PLA late signal circuitry using a specialized gap cell and PLA late signal circuitry using switched output'
[patent_app_type] => 1
[patent_app_number] => 8/603662
[patent_app_country] => US
[patent_app_date] => 1996-02-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 1966
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/717/05717344.pdf
[firstpage_image] =>[orig_patent_app_number] => 603662
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/603662 | PLA late signal circuitry using a specialized gap cell and PLA late signal circuitry using switched output | Feb 19, 1996 | Issued |
Array
(
[id] => 3822948
[patent_doc_number] => 05789943
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-04
[patent_title] => 'V.35 network terminator'
[patent_app_type] => 1
[patent_app_number] => 8/603738
[patent_app_country] => US
[patent_app_date] => 1996-02-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 25
[patent_no_of_words] => 4988
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 58
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/789/05789943.pdf
[firstpage_image] =>[orig_patent_app_number] => 603738
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/603738 | V.35 network terminator | Feb 19, 1996 | Issued |
| 08/603661 | PROGRAMMABLE LOGIC ARRAY AND METHOD FOR ITS DESIGN USING A THREE STEP APPROACH | Feb 19, 1996 | Abandoned |
Array
(
[id] => 3693676
[patent_doc_number] => 05691652
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-11-25
[patent_title] => 'Completion detection as a means for improving alpha soft-error resistance'
[patent_app_type] => 1
[patent_app_number] => 8/603977
[patent_app_country] => US
[patent_app_date] => 1996-02-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 6489
[patent_no_of_claims] => 11
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/691/05691652.pdf
[firstpage_image] =>[orig_patent_app_number] => 603977
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/603977 | Completion detection as a means for improving alpha soft-error resistance | Feb 19, 1996 | Issued |
Array
(
[id] => 3767063
[patent_doc_number] => 05742184
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-21
[patent_title] => 'Microprocessor having a compensated input buffer circuit'
[patent_app_type] => 1
[patent_app_number] => 8/603053
[patent_app_country] => US
[patent_app_date] => 1996-02-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 7793
[patent_no_of_claims] => 5
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/742/05742184.pdf
[firstpage_image] =>[orig_patent_app_number] => 603053
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/603053 | Microprocessor having a compensated input buffer circuit | Feb 15, 1996 | Issued |
Array
(
[id] => 4050218
[patent_doc_number] => 05909127
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-01
[patent_title] => 'Circuits with dynamically biased active loads'
[patent_app_type] => 1
[patent_app_number] => 8/601628
[patent_app_country] => US
[patent_app_date] => 1996-02-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 14
[patent_no_of_words] => 5454
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 9
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/909/05909127.pdf
[firstpage_image] =>[orig_patent_app_number] => 601628
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/601628 | Circuits with dynamically biased active loads | Feb 13, 1996 | Issued |
Array
(
[id] => 3999919
[patent_doc_number] => 05892371
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-04-06
[patent_title] => 'Gate oxide voltage limiting devices for digital circuits'
[patent_app_type] => 1
[patent_app_number] => 8/599878
[patent_app_country] => US
[patent_app_date] => 1996-02-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 6481
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 279
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/892/05892371.pdf
[firstpage_image] =>[orig_patent_app_number] => 599878
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/599878 | Gate oxide voltage limiting devices for digital circuits | Feb 11, 1996 | Issued |
Array
(
[id] => 3796381
[patent_doc_number] => 05841295
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-24
[patent_title] => 'Hybrid programmable logic device'
[patent_app_type] => 1
[patent_app_number] => 8/598766
[patent_app_country] => US
[patent_app_date] => 1996-02-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 13
[patent_no_of_words] => 6108
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/841/05841295.pdf
[firstpage_image] =>[orig_patent_app_number] => 598766
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/598766 | Hybrid programmable logic device | Feb 8, 1996 | Issued |
Array
(
[id] => 3848468
[patent_doc_number] => 05708373
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-01-13
[patent_title] => 'Boost circuit'
[patent_app_type] => 1
[patent_app_number] => 8/597371
[patent_app_country] => US
[patent_app_date] => 1996-02-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 2649
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/708/05708373.pdf
[firstpage_image] =>[orig_patent_app_number] => 597371
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/597371 | Boost circuit | Feb 7, 1996 | Issued |
Array
(
[id] => 3663432
[patent_doc_number] => 05627482
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-05-06
[patent_title] => 'Electronic digital clock distribution system'
[patent_app_type] => 1
[patent_app_number] => 8/598233
[patent_app_country] => US
[patent_app_date] => 1996-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/627/05627482.pdf
[firstpage_image] =>[orig_patent_app_number] => 598233
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/598233 | Electronic digital clock distribution system | Feb 6, 1996 | Issued |
Array
(
[id] => 3666685
[patent_doc_number] => 05656951
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-08-12
[patent_title] => 'Input circuit and method for holding data in mixed power supply mode'
[patent_app_type] => 1
[patent_app_number] => 8/596856
[patent_app_country] => US
[patent_app_date] => 1996-02-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/656/05656951.pdf
[firstpage_image] =>[orig_patent_app_number] => 596856
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/596856 | Input circuit and method for holding data in mixed power supply mode | Feb 4, 1996 | Issued |
Array
(
[id] => 3639802
[patent_doc_number] => 05610539
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-03-11
[patent_title] => 'Logic family for low voltage high-speed applications'
[patent_app_type] => 1
[patent_app_number] => 8/594063
[patent_app_country] => US
[patent_app_date] => 1996-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/610/05610539.pdf
[firstpage_image] =>[orig_patent_app_number] => 594063
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/594063 | Logic family for low voltage high-speed applications | Jan 29, 1996 | Issued |
Array
(
[id] => 3631347
[patent_doc_number] => 05621338
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-04-15
[patent_title] => 'High speed configuration independent programmable macrocell'
[patent_app_type] => 1
[patent_app_number] => 8/584105
[patent_app_country] => US
[patent_app_date] => 1996-01-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 4451
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/621/05621338.pdf
[firstpage_image] =>[orig_patent_app_number] => 584105
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/584105 | High speed configuration independent programmable macrocell | Jan 10, 1996 | Issued |
| 08/580855 | PROGRAMMABLE I/O CELL WITH DATA CONVERSION CAPABILITY | Dec 28, 1995 | Abandoned |
Array
(
[id] => 3884541
[patent_doc_number] => 05804986
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-08
[patent_title] => 'Memory in a programmable logic device'
[patent_app_type] => 1
[patent_app_number] => 8/580626
[patent_app_country] => US
[patent_app_date] => 1995-12-29
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/804/05804986.pdf
[firstpage_image] =>[orig_patent_app_number] => 580626
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/580626 | Memory in a programmable logic device | Dec 28, 1995 | Issued |
Array
(
[id] => 3982337
[patent_doc_number] => 05917337
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-29
[patent_title] => 'Programmable I/O cell with data conversion capability'
[patent_app_type] => 1
[patent_app_number] => 8/578201
[patent_app_country] => US
[patent_app_date] => 1995-12-29
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/917/05917337.pdf
[firstpage_image] =>[orig_patent_app_number] => 578201
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/578201 | Programmable I/O cell with data conversion capability | Dec 28, 1995 | Issued |
Array
(
[id] => 4055753
[patent_doc_number] => 05869982
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-09
[patent_title] => 'Programmable I/O cell with data conversion capability'
[patent_app_type] => 1
[patent_app_number] => 8/580770
[patent_app_country] => US
[patent_app_date] => 1995-12-29
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[pdf_file] => patents/05/869/05869982.pdf
[firstpage_image] =>[orig_patent_app_number] => 580770
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/580770 | Programmable I/O cell with data conversion capability | Dec 28, 1995 | Issued |
Array
(
[id] => 3766986
[patent_doc_number] => 05742179
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-21
[patent_title] => 'High speed programmable logic architecture'
[patent_app_type] => 1
[patent_app_number] => 8/580668
[patent_app_country] => US
[patent_app_date] => 1995-12-29
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[pdf_file] => patents/05/742/05742179.pdf
[firstpage_image] =>[orig_patent_app_number] => 580668
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/580668 | High speed programmable logic architecture | Dec 28, 1995 | Issued |