
Jon P. Santamauro
Examiner (ID: 13669)
| Most Active Art Unit | 2819 |
| Art Unit(s) | 2819, 2509, 2878 |
| Total Applications | 622 |
| Issued Applications | 539 |
| Pending Applications | 28 |
| Abandoned Applications | 55 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3604110
[patent_doc_number] => 05559451
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-09-24
[patent_title] => 'Bicmos push-pull type logic apparatus with voltage clamp circuit and clamp releasing circuit'
[patent_app_type] => 1
[patent_app_number] => 8/528647
[patent_app_country] => US
[patent_app_date] => 1995-09-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 24
[patent_no_of_words] => 4158
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/559/05559451.pdf
[firstpage_image] =>[orig_patent_app_number] => 528647
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/528647 | Bicmos push-pull type logic apparatus with voltage clamp circuit and clamp releasing circuit | Sep 6, 1995 | Issued |
Array
(
[id] => 3497744
[patent_doc_number] => 05537059
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-16
[patent_title] => 'Output circuit of semiconductor integrated circuit device'
[patent_app_type] => 1
[patent_app_number] => 8/523753
[patent_app_country] => US
[patent_app_date] => 1995-09-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 14
[patent_no_of_words] => 10988
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/537/05537059.pdf
[firstpage_image] =>[orig_patent_app_number] => 523753
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/523753 | Output circuit of semiconductor integrated circuit device | Sep 4, 1995 | Issued |
Array
(
[id] => 3639546
[patent_doc_number] => 05631576
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-05-20
[patent_title] => 'Programmable logic array integrated circuit devices with flexible carry chains'
[patent_app_type] => 1
[patent_app_number] => 8/522554
[patent_app_country] => US
[patent_app_date] => 1995-09-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2945
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 221
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/631/05631576.pdf
[firstpage_image] =>[orig_patent_app_number] => 522554
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/522554 | Programmable logic array integrated circuit devices with flexible carry chains | Aug 31, 1995 | Issued |
Array
(
[id] => 3625895
[patent_doc_number] => 05614842
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-03-25
[patent_title] => 'Semiconductor integrated circuit with buffer circuit and manufacturing method thereof'
[patent_app_type] => 1
[patent_app_number] => 8/522962
[patent_app_country] => US
[patent_app_date] => 1995-09-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 7637
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 221
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/614/05614842.pdf
[firstpage_image] =>[orig_patent_app_number] => 522962
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/522962 | Semiconductor integrated circuit with buffer circuit and manufacturing method thereof | Aug 31, 1995 | Issued |
Array
(
[id] => 3631334
[patent_doc_number] => 05621337
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-04-15
[patent_title] => 'Iterative logic circuit'
[patent_app_type] => 1
[patent_app_number] => 8/521348
[patent_app_country] => US
[patent_app_date] => 1995-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1768
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/621/05621337.pdf
[firstpage_image] =>[orig_patent_app_number] => 521348
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/521348 | Iterative logic circuit | Aug 29, 1995 | Issued |
Array
(
[id] => 3607998
[patent_doc_number] => 05578941
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-26
[patent_title] => 'Voltage compensating CMOS input buffer circuit'
[patent_app_type] => 1
[patent_app_number] => 8/518546
[patent_app_country] => US
[patent_app_date] => 1995-08-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 2359
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/578/05578941.pdf
[firstpage_image] =>[orig_patent_app_number] => 518546
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/518546 | Voltage compensating CMOS input buffer circuit | Aug 22, 1995 | Issued |
Array
(
[id] => 3639786
[patent_doc_number] => 05610538
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-03-11
[patent_title] => 'Buffer apparatus having a low output impedance'
[patent_app_type] => 1
[patent_app_number] => 8/516149
[patent_app_country] => US
[patent_app_date] => 1995-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 2616
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/610/05610538.pdf
[firstpage_image] =>[orig_patent_app_number] => 516149
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/516149 | Buffer apparatus having a low output impedance | Aug 16, 1995 | Issued |
Array
(
[id] => 3521094
[patent_doc_number] => 05576636
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-19
[patent_title] => 'Low power programmable logic arrays'
[patent_app_type] => 1
[patent_app_number] => 8/515248
[patent_app_country] => US
[patent_app_date] => 1995-08-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 2624
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 192
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/576/05576636.pdf
[firstpage_image] =>[orig_patent_app_number] => 515248
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/515248 | Low power programmable logic arrays | Aug 14, 1995 | Issued |
Array
(
[id] => 3558855
[patent_doc_number] => 05574389
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-12
[patent_title] => 'CMOS 3.3 volt output buffer with 5 volt protection'
[patent_app_type] => 1
[patent_app_number] => 8/513053
[patent_app_country] => US
[patent_app_date] => 1995-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 2975
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 432
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/574/05574389.pdf
[firstpage_image] =>[orig_patent_app_number] => 513053
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/513053 | CMOS 3.3 volt output buffer with 5 volt protection | Aug 8, 1995 | Issued |
Array
(
[id] => 3882226
[patent_doc_number] => 05825205
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-20
[patent_title] => 'Level-shift circuit for driving word lines of negative gate erasable type flash memory'
[patent_app_type] => 1
[patent_app_number] => 8/511446
[patent_app_country] => US
[patent_app_date] => 1995-08-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 18
[patent_no_of_words] => 10722
[patent_no_of_claims] => 48
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 332
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/825/05825205.pdf
[firstpage_image] =>[orig_patent_app_number] => 511446
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/511446 | Level-shift circuit for driving word lines of negative gate erasable type flash memory | Aug 3, 1995 | Issued |
Array
(
[id] => 3695363
[patent_doc_number] => 05604450
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-02-18
[patent_title] => 'High speed bidirectional signaling scheme'
[patent_app_type] => 1
[patent_app_number] => 8/508159
[patent_app_country] => US
[patent_app_date] => 1995-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 4007
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/604/05604450.pdf
[firstpage_image] =>[orig_patent_app_number] => 508159
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/508159 | High speed bidirectional signaling scheme | Jul 26, 1995 | Issued |
Array
(
[id] => 3742607
[patent_doc_number] => 05698994
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-16
[patent_title] => 'Data output circuit, intermediate potential setting circuit, and semiconductor integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 8/507943
[patent_app_country] => US
[patent_app_date] => 1995-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 30
[patent_no_of_words] => 14376
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 177
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/698/05698994.pdf
[firstpage_image] =>[orig_patent_app_number] => 507943
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/507943 | Data output circuit, intermediate potential setting circuit, and semiconductor integrated circuit | Jul 26, 1995 | Issued |
Array
(
[id] => 3604093
[patent_doc_number] => 05559450
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-09-24
[patent_title] => 'Field programmable gate array with multi-port RAM'
[patent_app_type] => 1
[patent_app_number] => 8/507957
[patent_app_country] => US
[patent_app_date] => 1995-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 4670
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/559/05559450.pdf
[firstpage_image] =>[orig_patent_app_number] => 507957
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/507957 | Field programmable gate array with multi-port RAM | Jul 26, 1995 | Issued |
Array
(
[id] => 3711749
[patent_doc_number] => 05654645
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-08-05
[patent_title] => 'Buffer with controlled hysteresis'
[patent_app_type] => 1
[patent_app_number] => 8/507849
[patent_app_country] => US
[patent_app_date] => 1995-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 18
[patent_no_of_words] => 9373
[patent_no_of_claims] => 40
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/654/05654645.pdf
[firstpage_image] =>[orig_patent_app_number] => 507849
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/507849 | Buffer with controlled hysteresis | Jul 26, 1995 | Issued |
Array
(
[id] => 3514637
[patent_doc_number] => 05587665
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-24
[patent_title] => 'Testing hot carrier induced degradation to fall and rise time of CMOS inverter circuits'
[patent_app_type] => 1
[patent_app_number] => 8/503760
[patent_app_country] => US
[patent_app_date] => 1995-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2672
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/587/05587665.pdf
[firstpage_image] =>[orig_patent_app_number] => 503760
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/503760 | Testing hot carrier induced degradation to fall and rise time of CMOS inverter circuits | Jul 17, 1995 | Issued |
| 08/497165 | PROGRAMMABLE LOGIC ARRAY INTEGRATED CIRCUITS WITH LAB BASED AND FUNCTION | Jun 29, 1995 | Abandoned |
Array
(
[id] => 3673343
[patent_doc_number] => 05600260
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-02-04
[patent_title] => 'Method and apparatus for hardening current steering logic to soft errors'
[patent_app_type] => 1
[patent_app_number] => 8/496651
[patent_app_country] => US
[patent_app_date] => 1995-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2972
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/600/05600260.pdf
[firstpage_image] =>[orig_patent_app_number] => 496651
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/496651 | Method and apparatus for hardening current steering logic to soft errors | Jun 28, 1995 | Issued |
| 08/496254 | DIGITAL LOGIC OUTPUT BUFFER INTERFACE FOR DIFFERENT SEMICONDUCTOR TECHNOLOGIES | Jun 27, 1995 | Abandoned |
Array
(
[id] => 3617813
[patent_doc_number] => 05565794
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-15
[patent_title] => 'Voltage range tolerant CMOS output buffer with reduced input capacitance'
[patent_app_type] => 1
[patent_app_number] => 8/494271
[patent_app_country] => US
[patent_app_date] => 1995-06-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 14
[patent_no_of_words] => 4364
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 215
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/565/05565794.pdf
[firstpage_image] =>[orig_patent_app_number] => 494271
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/494271 | Voltage range tolerant CMOS output buffer with reduced input capacitance | Jun 22, 1995 | Issued |
Array
(
[id] => 3625684
[patent_doc_number] => 05642059
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-06-24
[patent_title] => 'Bus driver circuit with overvoltage protection'
[patent_app_type] => 1
[patent_app_number] => 8/481548
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 1558
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 204
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/642/05642059.pdf
[firstpage_image] =>[orig_patent_app_number] => 481548
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/481548 | Bus driver circuit with overvoltage protection | Jun 6, 1995 | Issued |