Search

Jon P. Santamauro

Examiner (ID: 474)

Most Active Art Unit
2819
Art Unit(s)
2819, 2509, 2878
Total Applications
622
Issued Applications
539
Pending Applications
28
Abandoned Applications
55

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4103991 [patent_doc_number] => 06097217 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'MOS output buffer with overvoltage protection circuitry' [patent_app_type] => 1 [patent_app_number] => 9/210761 [patent_app_country] => US [patent_app_date] => 1998-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 30 [patent_no_of_words] => 14758 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 425 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/097/06097217.pdf [firstpage_image] =>[orig_patent_app_number] => 210761 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/210761
MOS output buffer with overvoltage protection circuitry Dec 13, 1998 Issued
Array ( [id] => 4077535 [patent_doc_number] => 06069496 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-30 [patent_title] => 'CMOS circuit technique for improved switching speed of single-ended and differential dynamic logic' [patent_app_type] => 1 [patent_app_number] => 9/207303 [patent_app_country] => US [patent_app_date] => 1998-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 7775 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/069/06069496.pdf [firstpage_image] =>[orig_patent_app_number] => 207303 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/207303
CMOS circuit technique for improved switching speed of single-ended and differential dynamic logic Dec 7, 1998 Issued
Array ( [id] => 4163864 [patent_doc_number] => 06107836 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Semiconductor integrated circuit device having power reduction mechanism' [patent_app_type] => 1 [patent_app_number] => 9/199199 [patent_app_country] => US [patent_app_date] => 1998-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 70 [patent_no_of_words] => 22866 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/107/06107836.pdf [firstpage_image] =>[orig_patent_app_number] => 199199 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/199199
Semiconductor integrated circuit device having power reduction mechanism Nov 24, 1998 Issued
Array ( [id] => 4412630 [patent_doc_number] => 06232793 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Switched backgate bias for FET' [patent_app_type] => 1 [patent_app_number] => 9/195460 [patent_app_country] => US [patent_app_date] => 1998-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 14192 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/232/06232793.pdf [firstpage_image] =>[orig_patent_app_number] => 195460 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/195460
Switched backgate bias for FET Nov 17, 1998 Issued
Array ( [id] => 4413329 [patent_doc_number] => 06172529 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Compound domino logic circuit having output noise elimination' [patent_app_type] => 1 [patent_app_number] => 9/161893 [patent_app_country] => US [patent_app_date] => 1998-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2300 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/172/06172529.pdf [firstpage_image] =>[orig_patent_app_number] => 161893 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/161893
Compound domino logic circuit having output noise elimination Sep 27, 1998 Issued
Array ( [id] => 4366866 [patent_doc_number] => 06191611 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Driver circuitry for programmable logic devices with hierarchical interconnection resources' [patent_app_type] => 1 [patent_app_number] => 9/160286 [patent_app_country] => US [patent_app_date] => 1998-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9203 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/191/06191611.pdf [firstpage_image] =>[orig_patent_app_number] => 160286 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/160286
Driver circuitry for programmable logic devices with hierarchical interconnection resources Sep 24, 1998 Issued
Array ( [id] => 4299535 [patent_doc_number] => 06236228 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Structure and method of repair of integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/152778 [patent_app_country] => US [patent_app_date] => 1998-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4343 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/236/06236228.pdf [firstpage_image] =>[orig_patent_app_number] => 152778 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/152778
Structure and method of repair of integrated circuits Sep 13, 1998 Issued
Array ( [id] => 4365160 [patent_doc_number] => 06169419 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Method and apparatus for reducing standby leakage current using a transistor stack effect' [patent_app_type] => 1 [patent_app_number] => 9/151177 [patent_app_country] => US [patent_app_date] => 1998-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6381 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/169/06169419.pdf [firstpage_image] =>[orig_patent_app_number] => 151177 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/151177
Method and apparatus for reducing standby leakage current using a transistor stack effect Sep 9, 1998 Issued
Array ( [id] => 4246322 [patent_doc_number] => 06091266 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Circuit arrangement for a digital circuit using differential logic' [patent_app_type] => 1 [patent_app_number] => 9/150689 [patent_app_country] => US [patent_app_date] => 1998-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1118 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/091/06091266.pdf [firstpage_image] =>[orig_patent_app_number] => 150689 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/150689
Circuit arrangement for a digital circuit using differential logic Sep 9, 1998 Issued
Array ( [id] => 3963145 [patent_doc_number] => 05936428 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Low power, high speed level shifter' [patent_app_type] => 1 [patent_app_number] => 9/146304 [patent_app_country] => US [patent_app_date] => 1998-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 2795 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/936/05936428.pdf [firstpage_image] =>[orig_patent_app_number] => 146304 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/146304
Low power, high speed level shifter Sep 2, 1998 Issued
Array ( [id] => 4225070 [patent_doc_number] => 06087854 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'High speed line driver with direct and complementary outputs' [patent_app_type] => 1 [patent_app_number] => 9/145793 [patent_app_country] => US [patent_app_date] => 1998-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 3 [patent_no_of_words] => 3774 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/087/06087854.pdf [firstpage_image] =>[orig_patent_app_number] => 145793 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/145793
High speed line driver with direct and complementary outputs Sep 1, 1998 Issued
Array ( [id] => 4365120 [patent_doc_number] => 06169416 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Programming architecture for field programmable gate array' [patent_app_type] => 1 [patent_app_number] => 9/145581 [patent_app_country] => US [patent_app_date] => 1998-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2881 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/169/06169416.pdf [firstpage_image] =>[orig_patent_app_number] => 145581 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/145581
Programming architecture for field programmable gate array Aug 31, 1998 Issued
Array ( [id] => 4197265 [patent_doc_number] => 06154062 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Semiconductor integrated circuits with power reduction mechanism' [patent_app_type] => 1 [patent_app_number] => 9/141563 [patent_app_country] => US [patent_app_date] => 1998-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 29 [patent_no_of_words] => 16124 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/154/06154062.pdf [firstpage_image] =>[orig_patent_app_number] => 141563 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/141563
Semiconductor integrated circuits with power reduction mechanism Aug 27, 1998 Issued
Array ( [id] => 3931270 [patent_doc_number] => 05945844 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Threshold voltage scalable buffer with reference level' [patent_app_type] => 1 [patent_app_number] => 9/137206 [patent_app_country] => US [patent_app_date] => 1998-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4312 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/945/05945844.pdf [firstpage_image] =>[orig_patent_app_number] => 137206 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/137206
Threshold voltage scalable buffer with reference level Aug 19, 1998 Issued
Array ( [id] => 4139410 [patent_doc_number] => 06147508 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Power consumption control mechanism and method therefor' [patent_app_type] => 1 [patent_app_number] => 9/137776 [patent_app_country] => US [patent_app_date] => 1998-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5115 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/147/06147508.pdf [firstpage_image] =>[orig_patent_app_number] => 137776 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/137776
Power consumption control mechanism and method therefor Aug 19, 1998 Issued
Array ( [id] => 4134506 [patent_doc_number] => 06127849 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Simultaneous bi-directional input/output (I/O) circuit' [patent_app_type] => 1 [patent_app_number] => 9/131987 [patent_app_country] => US [patent_app_date] => 1998-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 8398 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/127/06127849.pdf [firstpage_image] =>[orig_patent_app_number] => 131987 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/131987
Simultaneous bi-directional input/output (I/O) circuit Aug 10, 1998 Issued
Array ( [id] => 4121775 [patent_doc_number] => 06046604 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-04 [patent_title] => 'Semiconductor integrated circuit device having power reduction mechanism' [patent_app_type] => 1 [patent_app_number] => 9/123480 [patent_app_country] => US [patent_app_date] => 1998-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 59 [patent_no_of_words] => 18600 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/046/06046604.pdf [firstpage_image] =>[orig_patent_app_number] => 123480 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/123480
Semiconductor integrated circuit device having power reduction mechanism Jul 27, 1998 Issued
Array ( [id] => 4197798 [patent_doc_number] => 06130556 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-10 [patent_title] => 'Integrated circuit I/O buffer with 5V well and passive gate voltage' [patent_app_type] => 1 [patent_app_number] => 9/098099 [patent_app_country] => US [patent_app_date] => 1998-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5965 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/130/06130556.pdf [firstpage_image] =>[orig_patent_app_number] => 098099 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/098099
Integrated circuit I/O buffer with 5V well and passive gate voltage Jun 15, 1998 Issued
Array ( [id] => 4096996 [patent_doc_number] => 06133759 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Decoupled reset dynamic logic circuit' [patent_app_type] => 1 [patent_app_number] => 9/097794 [patent_app_country] => US [patent_app_date] => 1998-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4940 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/133/06133759.pdf [firstpage_image] =>[orig_patent_app_number] => 097794 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/097794
Decoupled reset dynamic logic circuit Jun 15, 1998 Issued
Array ( [id] => 3963064 [patent_doc_number] => 05936425 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Tri-statable input/output circuitry for programmable logic' [patent_app_type] => 1 [patent_app_number] => 9/096250 [patent_app_country] => US [patent_app_date] => 1998-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2706 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/936/05936425.pdf [firstpage_image] =>[orig_patent_app_number] => 096250 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/096250
Tri-statable input/output circuitry for programmable logic Jun 10, 1998 Issued
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