Jon P. Santamauro

Array ( [id] => 3628703 [patent_doc_number] => 05612634 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-18 [patent_title] => 'Circuit for sensing whether or not an add-in board is inserted into a bus connector of a mother board' [patent_app_type] => 1 [patent_app_number] => 8/311951 [patent_app_country] => US [patent_app_date] => 1994-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4640 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/612/05612634.pdf [firstpage_image] =>[orig_patent_app_number] => 311951 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3107854 [patent_doc_number] => 05448181 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-05 [patent_title] => 'Output buffer circuit having reduced switching noise' [patent_app_type] => 1 [patent_app_number] => 8/310203 [patent_app_country] => US [patent_app_date] => 1994-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 1563 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/448/05448181.pdf [firstpage_image] =>[orig_patent_app_number] => 310203 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3586880 [patent_doc_number] => 05498979 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-12 [patent_title] => 'Adaptive programming method for antifuse technology' [patent_app_type] => 1 [patent_app_number] => 8/310111 [patent_app_country] => US [patent_app_date] => 1994-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5109 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/498/05498979.pdf [firstpage_image] =>[orig_patent_app_number] => 310111 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3530632 [patent_doc_number] => 05528171 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-18 [patent_title] => 'ECL-to-CMOS signal level converter' [patent_app_type] => 1 [patent_app_number] => 8/307466 [patent_app_country] => US [patent_app_date] => 1994-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3455 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/528/05528171.pdf [firstpage_image] =>[orig_patent_app_number] => 307466 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3521329 [patent_doc_number] => 05486777 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-23 [patent_title] => 'Low power differential receiver input circuit' [patent_app_type] => 1 [patent_app_number] => 8/301462 [patent_app_country] => US [patent_app_date] => 1994-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3192 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/486/05486777.pdf [firstpage_image] =>[orig_patent_app_number] => 301462 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3488353 [patent_doc_number] => 05446402 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-29 [patent_title] => 'Noise tolerant code setting circuit' [patent_app_type] => 1 [patent_app_number] => 8/298459 [patent_app_country] => US [patent_app_date] => 1994-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1647 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 308 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/446/05446402.pdf [firstpage_image] =>[orig_patent_app_number] => 298459 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3625965 [patent_doc_number] => 05614847 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-25 [patent_title] => 'Semiconductor integrated circuit device having power reduction mechanism' [patent_app_type] => 1 [patent_app_number] => 8/294055 [patent_app_country] => US [patent_app_date] => 1994-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 70 [patent_no_of_words] => 22837 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/614/05614847.pdf [firstpage_image] =>[orig_patent_app_number] => 294055 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3494801 [patent_doc_number] => 05471155 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-28 [patent_title] => 'User programmable product term width expander' [patent_app_type] => 1 [patent_app_number] => 8/293280 [patent_app_country] => US [patent_app_date] => 1994-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3946 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/471/05471155.pdf [firstpage_image] =>[orig_patent_app_number] => 293280 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3117460 [patent_doc_number] => 05414376 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-09 [patent_title] => 'Programmable logic device macrocell having exclusive lines for feedback and external input, and a node which is selectively shared for registered output and external input' [patent_app_type] => 1 [patent_app_number] => 8/289960 [patent_app_country] => US [patent_app_date] => 1994-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1850 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 313 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/414/05414376.pdf [firstpage_image] =>[orig_patent_app_number] => 289960 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3597803 [patent_doc_number] => 05521536 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-28 [patent_title] => 'Integrated circuit device having different signal transfer circuits for wirings with different lengths' [patent_app_type] => 1 [patent_app_number] => 8/286270 [patent_app_country] => US [patent_app_date] => 1994-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 9090 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/521/05521536.pdf [firstpage_image] =>[orig_patent_app_number] => 286270 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3619794 [patent_doc_number] => 05510732 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-23 [patent_title] => 'Synchronizer circuit and method for reducing the occurrence of metastability conditions in digital systems' [patent_app_type] => 1 [patent_app_number] => 8/285366 [patent_app_country] => US [patent_app_date] => 1994-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3703 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/510/05510732.pdf [firstpage_image] =>[orig_patent_app_number] => 285366 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3572113 [patent_doc_number] => 05485105 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-16 [patent_title] => 'Apparatus and method for programming field programmable arrays' [patent_app_type] => 1 [patent_app_number] => 8/283469 [patent_app_country] => US [patent_app_date] => 1994-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1917 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/485/05485105.pdf [firstpage_image] =>[orig_patent_app_number] => 283469 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3122457 [patent_doc_number] => 05450026 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-12 [patent_title] => 'Current mode driver for differential bus' [patent_app_type] => 1 [patent_app_number] => 8/281057 [patent_app_country] => US [patent_app_date] => 1994-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3940 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/450/05450026.pdf [firstpage_image] =>[orig_patent_app_number] => 281057 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3526625 [patent_doc_number] => 05489859 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-06 [patent_title] => 'CMOS output circuit with high speed high impedance mode' [patent_app_type] => 1 [patent_app_number] => 8/278067 [patent_app_country] => US [patent_app_date] => 1994-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5845 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 322 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/489/05489859.pdf [firstpage_image] =>[orig_patent_app_number] => 278067 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3669908 [patent_doc_number] => 05598111 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-28 [patent_title] => 'Delay circuit for digital signal processing' [patent_app_type] => 1 [patent_app_number] => 8/266589 [patent_app_country] => US [patent_app_date] => 1994-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 3715 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 437 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/598/05598111.pdf [firstpage_image] =>[orig_patent_app_number] => 266589 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3592016 [patent_doc_number] => 05552723 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-03 [patent_title] => 'CMOS output circuit compensating for back-gate bias effects' [patent_app_type] => 1 [patent_app_number] => 8/264853 [patent_app_country] => US [patent_app_date] => 1994-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 76 [patent_no_of_words] => 10693 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/552/05552723.pdf [firstpage_image] =>[orig_patent_app_number] => 264853 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3554651 [patent_doc_number] => 05548225 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-20 [patent_title] => 'Block specific spare circuit' [patent_app_type] => 1 [patent_app_number] => 8/249499 [patent_app_country] => US [patent_app_date] => 1994-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5374 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/548/05548225.pdf [firstpage_image] =>[orig_patent_app_number] => 249499 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3499925 [patent_doc_number] => 05508636 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-16 [patent_title] => 'Electronic system organised as an array of cells' [patent_app_type] => 1 [patent_app_number] => 8/246698 [patent_app_country] => US [patent_app_date] => 1994-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2609 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/508/05508636.pdf [firstpage_image] =>[orig_patent_app_number] => 246698 [rel_patent_id] =>[rel_patent_doc_number] =>)