Search

Jon P. Santamauro

Examiner (ID: 474)

Most Active Art Unit
2819
Art Unit(s)
2819, 2509, 2878
Total Applications
622
Issued Applications
539
Pending Applications
28
Abandoned Applications
55

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4077409 [patent_doc_number] => 06069487 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-30 [patent_title] => 'Programmable logic device circuitry for improving multiplier speed and/or efficiency' [patent_app_type] => 1 [patent_app_number] => 9/094387 [patent_app_country] => US [patent_app_date] => 1998-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 7874 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/069/06069487.pdf [firstpage_image] =>[orig_patent_app_number] => 094387 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/094387
Programmable logic device circuitry for improving multiplier speed and/or efficiency Jun 8, 1998 Issued
Array ( [id] => 4255689 [patent_doc_number] => 06137316 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Integrated circuit with improved off chip drivers' [patent_app_type] => 1 [patent_app_number] => 9/093797 [patent_app_country] => US [patent_app_date] => 1998-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 5579 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/137/06137316.pdf [firstpage_image] =>[orig_patent_app_number] => 093797 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/093797
Integrated circuit with improved off chip drivers Jun 8, 1998 Issued
Array ( [id] => 4165233 [patent_doc_number] => 06114877 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Timing circuit utilizing a clock tree as a delay device' [patent_app_type] => 1 [patent_app_number] => 9/090678 [patent_app_country] => US [patent_app_date] => 1998-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2315 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/114/06114877.pdf [firstpage_image] =>[orig_patent_app_number] => 090678 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/090678
Timing circuit utilizing a clock tree as a delay device Jun 2, 1998 Issued
Array ( [id] => 4134478 [patent_doc_number] => 06127847 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'High-speed bipolar-to-CMOS logic converter circuit' [patent_app_type] => 1 [patent_app_number] => 9/088380 [patent_app_country] => US [patent_app_date] => 1998-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3241 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/127/06127847.pdf [firstpage_image] =>[orig_patent_app_number] => 088380 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/088380
High-speed bipolar-to-CMOS logic converter circuit May 31, 1998 Issued
Array ( [id] => 4303387 [patent_doc_number] => 06184711 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Low impact signal buffering in integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/086184 [patent_app_country] => US [patent_app_date] => 1998-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3858 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/184/06184711.pdf [firstpage_image] =>[orig_patent_app_number] => 086184 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/086184
Low impact signal buffering in integrated circuits May 27, 1998 Issued
Array ( [id] => 4182106 [patent_doc_number] => 06084429 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'PLD having a window pane architecture with segmented and staggered interconnect wiring between logic block arrays' [patent_app_type] => 1 [patent_app_number] => 9/066076 [patent_app_country] => US [patent_app_date] => 1998-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 2079 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/084/06084429.pdf [firstpage_image] =>[orig_patent_app_number] => 066076 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/066076
PLD having a window pane architecture with segmented and staggered interconnect wiring between logic block arrays Apr 23, 1998 Issued
90/004968 IMPEDANCE EMULATOR Apr 15, 1998 Issued
Array ( [id] => 4189156 [patent_doc_number] => 06020754 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'Look up table threshold gates' [patent_app_type] => 1 [patent_app_number] => 9/050375 [patent_app_country] => US [patent_app_date] => 1998-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3530 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/020/06020754.pdf [firstpage_image] =>[orig_patent_app_number] => 050375 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/050375
Look up table threshold gates Mar 30, 1998 Issued
Array ( [id] => 4153998 [patent_doc_number] => 06064229 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'Voltage translating buffer based on low voltage technology' [patent_app_type] => 1 [patent_app_number] => 9/048382 [patent_app_country] => US [patent_app_date] => 1998-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3572 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/064/06064229.pdf [firstpage_image] =>[orig_patent_app_number] => 048382 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/048382
Voltage translating buffer based on low voltage technology Mar 25, 1998 Issued
Array ( [id] => 4189204 [patent_doc_number] => 06020757 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'Slew rate selection circuit for a programmable device' [patent_app_type] => 1 [patent_app_number] => 9/047177 [patent_app_country] => US [patent_app_date] => 1998-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5306 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/020/06020757.pdf [firstpage_image] =>[orig_patent_app_number] => 047177 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/047177
Slew rate selection circuit for a programmable device Mar 23, 1998 Issued
Array ( [id] => 4153957 [patent_doc_number] => 06064226 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'Multiple input/output level interface input receiver' [patent_app_type] => 1 [patent_app_number] => 9/044198 [patent_app_country] => US [patent_app_date] => 1998-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4191 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/064/06064226.pdf [firstpage_image] =>[orig_patent_app_number] => 044198 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/044198
Multiple input/output level interface input receiver Mar 16, 1998 Issued
Array ( [id] => 4214053 [patent_doc_number] => 06028450 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Programmable input/output circuit with pull-up bias control' [patent_app_type] => 1 [patent_app_number] => 9/040497 [patent_app_country] => US [patent_app_date] => 1998-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 7302 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/028/06028450.pdf [firstpage_image] =>[orig_patent_app_number] => 040497 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/040497
Programmable input/output circuit with pull-up bias control Mar 16, 1998 Issued
Array ( [id] => 4245671 [patent_doc_number] => 06081132 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'High voltage drive output buffer for low Voltage integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/038680 [patent_app_country] => US [patent_app_date] => 1998-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1998 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/081/06081132.pdf [firstpage_image] =>[orig_patent_app_number] => 038680 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/038680
High voltage drive output buffer for low Voltage integrated circuits Mar 8, 1998 Issued
Array ( [id] => 4189191 [patent_doc_number] => 06020756 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'Multiplexer enhanced configurable logic block' [patent_app_type] => 1 [patent_app_number] => 9/034892 [patent_app_country] => US [patent_app_date] => 1998-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 6375 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/020/06020756.pdf [firstpage_image] =>[orig_patent_app_number] => 034892 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/034892
Multiplexer enhanced configurable logic block Mar 2, 1998 Issued
Array ( [id] => 4110230 [patent_doc_number] => 06051988 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Pulse width controlling logic circuit' [patent_app_type] => 1 [patent_app_number] => 9/033197 [patent_app_country] => US [patent_app_date] => 1998-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 8294 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/051/06051988.pdf [firstpage_image] =>[orig_patent_app_number] => 033197 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/033197
Pulse width controlling logic circuit Mar 1, 1998 Issued
Array ( [id] => 4259946 [patent_doc_number] => 06208162 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Technique for preconditioning I/Os during reconfiguration' [patent_app_type] => 1 [patent_app_number] => 9/026885 [patent_app_country] => US [patent_app_date] => 1998-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7146 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/208/06208162.pdf [firstpage_image] =>[orig_patent_app_number] => 026885 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/026885
Technique for preconditioning I/Os during reconfiguration Feb 18, 1998 Issued
Array ( [id] => 3940976 [patent_doc_number] => 05939897 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Method and apparatus for testing quiescent current in integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/022305 [patent_app_country] => US [patent_app_date] => 1998-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2266 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/939/05939897.pdf [firstpage_image] =>[orig_patent_app_number] => 022305 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/022305
Method and apparatus for testing quiescent current in integrated circuits Feb 10, 1998 Issued
Array ( [id] => 4302390 [patent_doc_number] => 06181158 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Configuration logic to eliminate signal contention during reconfiguration' [patent_app_type] => 1 [patent_app_number] => 9/018277 [patent_app_country] => US [patent_app_date] => 1998-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2341 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/181/06181158.pdf [firstpage_image] =>[orig_patent_app_number] => 018277 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/018277
Configuration logic to eliminate signal contention during reconfiguration Feb 3, 1998 Issued
Array ( [id] => 4141767 [patent_doc_number] => 06121796 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Power-saving dynamic circuit' [patent_app_type] => 1 [patent_app_number] => 9/014295 [patent_app_country] => US [patent_app_date] => 1998-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2217 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/121/06121796.pdf [firstpage_image] =>[orig_patent_app_number] => 014295 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/014295
Power-saving dynamic circuit Jan 26, 1998 Issued
Array ( [id] => 3919914 [patent_doc_number] => 06002272 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Tri-rail domino circuit' [patent_app_type] => 1 [patent_app_number] => 8/997071 [patent_app_country] => US [patent_app_date] => 1997-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4284 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/002/06002272.pdf [firstpage_image] =>[orig_patent_app_number] => 997071 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/997071
Tri-rail domino circuit Dec 22, 1997 Issued
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