Search

Jon P. Santamauro

Examiner (ID: 474)

Most Active Art Unit
2819
Art Unit(s)
2819, 2509, 2878
Total Applications
622
Issued Applications
539
Pending Applications
28
Abandoned Applications
55

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4125250 [patent_doc_number] => 06072331 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Amplifier for active terminator' [patent_app_type] => 1 [patent_app_number] => 8/997291 [patent_app_country] => US [patent_app_date] => 1997-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4403 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/072/06072331.pdf [firstpage_image] =>[orig_patent_app_number] => 997291 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/997291
Amplifier for active terminator Dec 22, 1997 Issued
Array ( [id] => 4413218 [patent_doc_number] => 06172519 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Bus-hold circuit having a defined state during set-up of an in-system programmable device' [patent_app_type] => 1 [patent_app_number] => 8/993596 [patent_app_country] => US [patent_app_date] => 1997-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4198 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/172/06172519.pdf [firstpage_image] =>[orig_patent_app_number] => 993596 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/993596
Bus-hold circuit having a defined state during set-up of an in-system programmable device Dec 17, 1997 Issued
Array ( [id] => 4110629 [patent_doc_number] => 06100712 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Output driver circuit with jump start for current sink on demand' [patent_app_type] => 1 [patent_app_number] => 8/992290 [patent_app_country] => US [patent_app_date] => 1997-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3492 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 324 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/100/06100712.pdf [firstpage_image] =>[orig_patent_app_number] => 992290 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/992290
Output driver circuit with jump start for current sink on demand Dec 16, 1997 Issued
Array ( [id] => 4058991 [patent_doc_number] => 05933024 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'ECL to CMOS level translator using delayed feedback for high speed BICMOS applications' [patent_app_type] => 1 [patent_app_number] => 8/990883 [patent_app_country] => US [patent_app_date] => 1997-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3511 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/933/05933024.pdf [firstpage_image] =>[orig_patent_app_number] => 990883 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/990883
ECL to CMOS level translator using delayed feedback for high speed BICMOS applications Dec 15, 1997 Issued
Array ( [id] => 3956769 [patent_doc_number] => 05977795 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Enhanced low voltage TTL interface' [patent_app_type] => 1 [patent_app_number] => 8/987678 [patent_app_country] => US [patent_app_date] => 1997-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 4407 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/977/05977795.pdf [firstpage_image] =>[orig_patent_app_number] => 987678 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/987678
Enhanced low voltage TTL interface Dec 8, 1997 Issued
Array ( [id] => 4115176 [patent_doc_number] => 06057706 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Field programmable gate array with integrated debugging facilities' [patent_app_type] => 1 [patent_app_number] => 8/985372 [patent_app_country] => US [patent_app_date] => 1997-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 3357 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/057/06057706.pdf [firstpage_image] =>[orig_patent_app_number] => 985372 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/985372
Field programmable gate array with integrated debugging facilities Dec 3, 1997 Issued
Array ( [id] => 4303287 [patent_doc_number] => 06184705 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Techniques for programming programmable logic array devices' [patent_app_type] => 1 [patent_app_number] => 8/982964 [patent_app_country] => US [patent_app_date] => 1997-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 6050 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/184/06184705.pdf [firstpage_image] =>[orig_patent_app_number] => 982964 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/982964
Techniques for programming programmable logic array devices Dec 1, 1997 Issued
Array ( [id] => 3944549 [patent_doc_number] => 05872462 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-16 [patent_title] => 'Programmable logic array and method for its design using a three step approach' [patent_app_type] => 1 [patent_app_number] => 8/978650 [patent_app_country] => US [patent_app_date] => 1997-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1394 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/872/05872462.pdf [firstpage_image] =>[orig_patent_app_number] => 978650 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/978650
Programmable logic array and method for its design using a three step approach Nov 25, 1997 Issued
Array ( [id] => 3946421 [patent_doc_number] => 05973514 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => '1.5V bootstrapped all-N-logic true-single-phase CMOS dynamic logic circuit suitable for low supply voltage and high speed pipelined system operation' [patent_app_type] => 1 [patent_app_number] => 8/977076 [patent_app_country] => US [patent_app_date] => 1997-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 4196 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 489 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/973/05973514.pdf [firstpage_image] =>[orig_patent_app_number] => 977076 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/977076
1.5V bootstrapped all-N-logic true-single-phase CMOS dynamic logic circuit suitable for low supply voltage and high speed pipelined system operation Nov 23, 1997 Issued
Array ( [id] => 4077523 [patent_doc_number] => 06069495 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-30 [patent_title] => 'High-speed logic embodied differential dynamic CMOS true single phase clock latches and flip-flops with single transistor clock latches' [patent_app_type] => 1 [patent_app_number] => 8/976190 [patent_app_country] => US [patent_app_date] => 1997-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 5130 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/069/06069495.pdf [firstpage_image] =>[orig_patent_app_number] => 976190 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/976190
High-speed logic embodied differential dynamic CMOS true single phase clock latches and flip-flops with single transistor clock latches Nov 20, 1997 Issued
Array ( [id] => 4204997 [patent_doc_number] => 06014036 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-11 [patent_title] => 'Bidirectional data transfer path having increased bandwidth' [patent_app_type] => 1 [patent_app_number] => 8/975368 [patent_app_country] => US [patent_app_date] => 1997-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 6080 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/014/06014036.pdf [firstpage_image] =>[orig_patent_app_number] => 975368 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/975368
Bidirectional data transfer path having increased bandwidth Nov 19, 1997 Issued
Array ( [id] => 4125304 [patent_doc_number] => 06072335 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Inverter control circuit' [patent_app_type] => 1 [patent_app_number] => 8/972791 [patent_app_country] => US [patent_app_date] => 1997-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4584 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/072/06072335.pdf [firstpage_image] =>[orig_patent_app_number] => 972791 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/972791
Inverter control circuit Nov 17, 1997 Issued
Array ( [id] => 4005189 [patent_doc_number] => 05986470 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Programmable logic array integrated circuit devices' [patent_app_type] => 1 [patent_app_number] => 8/970830 [patent_app_country] => US [patent_app_date] => 1997-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12864 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/986/05986470.pdf [firstpage_image] =>[orig_patent_app_number] => 970830 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/970830
Programmable logic array integrated circuit devices Nov 13, 1997 Issued
Array ( [id] => 4077422 [patent_doc_number] => 06069488 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-30 [patent_title] => 'Programmable logic device with versatile exclusive or architecture' [patent_app_type] => 1 [patent_app_number] => 8/970997 [patent_app_country] => US [patent_app_date] => 1997-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4699 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/069/06069488.pdf [firstpage_image] =>[orig_patent_app_number] => 970997 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/970997
Programmable logic device with versatile exclusive or architecture Nov 13, 1997 Issued
Array ( [id] => 3817788 [patent_doc_number] => 05811989 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'Programmable I/O cell with data conversion capability' [patent_app_type] => 1 [patent_app_number] => 8/967435 [patent_app_country] => US [patent_app_date] => 1997-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 8222 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/811/05811989.pdf [firstpage_image] =>[orig_patent_app_number] => 967435 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/967435
Programmable I/O cell with data conversion capability Nov 10, 1997 Issued
Array ( [id] => 4028888 [patent_doc_number] => 05926038 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Two-phase dynamic logic circuits for gallium arsenide complementary HIGFET fabrication' [patent_app_type] => 1 [patent_app_number] => 8/967133 [patent_app_country] => US [patent_app_date] => 1997-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 6889 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926038.pdf [firstpage_image] =>[orig_patent_app_number] => 967133 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/967133
Two-phase dynamic logic circuits for gallium arsenide complementary HIGFET fabrication Nov 9, 1997 Issued
Array ( [id] => 4199642 [patent_doc_number] => 06043684 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'Method and apparatus for reducing skew between input signals and clock signals within an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/960584 [patent_app_country] => US [patent_app_date] => 1997-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 7014 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/043/06043684.pdf [firstpage_image] =>[orig_patent_app_number] => 960584 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/960584
Method and apparatus for reducing skew between input signals and clock signals within an integrated circuit Oct 28, 1997 Issued
Array ( [id] => 4040471 [patent_doc_number] => 05994920 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Half-full flag generator for synchronous FIFOs' [patent_app_type] => 1 [patent_app_number] => 8/955809 [patent_app_country] => US [patent_app_date] => 1997-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3080 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/994/05994920.pdf [firstpage_image] =>[orig_patent_app_number] => 955809 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/955809
Half-full flag generator for synchronous FIFOs Oct 21, 1997 Issued
Array ( [id] => 4019396 [patent_doc_number] => 05963053 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Self-biasing CMOS PECL receiver with wide common-mode range and multi-level-transmit to binary decoder' [patent_app_type] => 1 [patent_app_number] => 8/947430 [patent_app_country] => US [patent_app_date] => 1997-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5470 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 333 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/963/05963053.pdf [firstpage_image] =>[orig_patent_app_number] => 947430 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/947430
Self-biasing CMOS PECL receiver with wide common-mode range and multi-level-transmit to binary decoder Oct 8, 1997 Issued
Array ( [id] => 3931225 [patent_doc_number] => 05945841 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Block segmentation of configuration lines for fault tolerant programmable logic device' [patent_app_type] => 1 [patent_app_number] => 8/941428 [patent_app_country] => US [patent_app_date] => 1997-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4993 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/945/05945841.pdf [firstpage_image] =>[orig_patent_app_number] => 941428 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/941428
Block segmentation of configuration lines for fault tolerant programmable logic device Sep 29, 1997 Issued
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