
Jon P. Santamauro
Examiner (ID: 474)
| Most Active Art Unit | 2819 |
| Art Unit(s) | 2819, 2509, 2878 |
| Total Applications | 622 |
| Issued Applications | 539 |
| Pending Applications | 28 |
| Abandoned Applications | 55 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4125250
[patent_doc_number] => 06072331
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-06
[patent_title] => 'Amplifier for active terminator'
[patent_app_type] => 1
[patent_app_number] => 8/997291
[patent_app_country] => US
[patent_app_date] => 1997-12-23
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[pdf_file] => patents/06/072/06072331.pdf
[firstpage_image] =>[orig_patent_app_number] => 997291
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/997291 | Amplifier for active terminator | Dec 22, 1997 | Issued |
Array
(
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[patent_kind] => NA
[patent_issue_date] => 2001-01-09
[patent_title] => 'Bus-hold circuit having a defined state during set-up of an in-system programmable device'
[patent_app_type] => 1
[patent_app_number] => 8/993596
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Array
(
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[patent_issue_date] => 2000-08-08
[patent_title] => 'Output driver circuit with jump start for current sink on demand'
[patent_app_type] => 1
[patent_app_number] => 8/992290
[patent_app_country] => US
[patent_app_date] => 1997-12-17
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[patent_drawing_sheets_cnt] => 2
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Array
(
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[patent_kind] => NA
[patent_issue_date] => 1999-08-03
[patent_title] => 'ECL to CMOS level translator using delayed feedback for high speed BICMOS applications'
[patent_app_type] => 1
[patent_app_number] => 8/990883
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[patent_app_date] => 1997-12-16
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/990883 | ECL to CMOS level translator using delayed feedback for high speed BICMOS applications | Dec 15, 1997 | Issued |
Array
(
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[patent_issue_date] => 1999-11-02
[patent_title] => 'Enhanced low voltage TTL interface'
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[patent_app_number] => 8/987678
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[patent_app_date] => 1997-12-09
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Array
(
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[patent_issue_date] => 2000-05-02
[patent_title] => 'Field programmable gate array with integrated debugging facilities'
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[patent_app_number] => 8/985372
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[firstpage_image] =>[orig_patent_app_number] => 985372
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/985372 | Field programmable gate array with integrated debugging facilities | Dec 3, 1997 | Issued |
Array
(
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[patent_title] => 'Techniques for programming programmable logic array devices'
[patent_app_type] => 1
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/982964 | Techniques for programming programmable logic array devices | Dec 1, 1997 | Issued |
Array
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[patent_title] => 'Programmable logic array and method for its design using a three step approach'
[patent_app_type] => 1
[patent_app_number] => 8/978650
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Array
(
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[patent_issue_date] => 1999-10-26
[patent_title] => '1.5V bootstrapped all-N-logic true-single-phase CMOS dynamic logic circuit suitable for low supply voltage and high speed pipelined system operation'
[patent_app_type] => 1
[patent_app_number] => 8/977076
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/977076 | 1.5V bootstrapped all-N-logic true-single-phase CMOS dynamic logic circuit suitable for low supply voltage and high speed pipelined system operation | Nov 23, 1997 | Issued |
Array
(
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[patent_title] => 'High-speed logic embodied differential dynamic CMOS true single phase clock latches and flip-flops with single transistor clock latches'
[patent_app_type] => 1
[patent_app_number] => 8/976190
[patent_app_country] => US
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Array
(
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[patent_title] => 'Bidirectional data transfer path having increased bandwidth'
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[patent_app_number] => 8/975368
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/975368 | Bidirectional data transfer path having increased bandwidth | Nov 19, 1997 | Issued |
Array
(
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[patent_title] => 'Inverter control circuit'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/972791 | Inverter control circuit | Nov 17, 1997 | Issued |
Array
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Array
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Array
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Array
(
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Array
(
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Array
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