Search

Jon P. Santamauro

Examiner (ID: 474)

Most Active Art Unit
2819
Art Unit(s)
2819, 2509, 2878
Total Applications
622
Issued Applications
539
Pending Applications
28
Abandoned Applications
55

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4189181 [patent_doc_number] => 06020755 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'Hybrid programmable gate arrays' [patent_app_type] => 1 [patent_app_number] => 8/938550 [patent_app_country] => US [patent_app_date] => 1997-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2993 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/020/06020755.pdf [firstpage_image] =>[orig_patent_app_number] => 938550 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/938550
Hybrid programmable gate arrays Sep 25, 1997 Issued
Array ( [id] => 3991761 [patent_doc_number] => 05959468 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Buffer for static in/static out dynamic speed' [patent_app_type] => 1 [patent_app_number] => 8/938131 [patent_app_country] => US [patent_app_date] => 1997-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 10052 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/959/05959468.pdf [firstpage_image] =>[orig_patent_app_number] => 938131 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/938131
Buffer for static in/static out dynamic speed Sep 25, 1997 Issued
Array ( [id] => 4032340 [patent_doc_number] => 05883524 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-16 [patent_title] => 'Low overhead memory designs for IC terminals' [patent_app_type] => 1 [patent_app_number] => 8/933896 [patent_app_country] => US [patent_app_date] => 1997-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 52 [patent_no_of_words] => 11558 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/883/05883524.pdf [firstpage_image] =>[orig_patent_app_number] => 933896 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/933896
Low overhead memory designs for IC terminals Sep 18, 1997 Issued
Array ( [id] => 3767270 [patent_doc_number] => 05852364 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-22 [patent_title] => 'System and method for testing integrated circuits connected together' [patent_app_type] => 1 [patent_app_number] => 8/933854 [patent_app_country] => US [patent_app_date] => 1997-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 52 [patent_no_of_words] => 11567 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/852/05852364.pdf [firstpage_image] =>[orig_patent_app_number] => 933854 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/933854
System and method for testing integrated circuits connected together Sep 18, 1997 Issued
Array ( [id] => 3963109 [patent_doc_number] => 05936427 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Three-input exclusive NOR circuit' [patent_app_type] => 1 [patent_app_number] => 8/931891 [patent_app_country] => US [patent_app_date] => 1997-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 5301 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 647 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/936/05936427.pdf [firstpage_image] =>[orig_patent_app_number] => 931891 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/931891
Three-input exclusive NOR circuit Sep 16, 1997 Issued
Array ( [id] => 4199628 [patent_doc_number] => 06043683 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'Output pad circuit using control signal' [patent_app_type] => 1 [patent_app_number] => 8/931883 [patent_app_country] => US [patent_app_date] => 1997-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2424 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/043/06043683.pdf [firstpage_image] =>[orig_patent_app_number] => 931883 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/931883
Output pad circuit using control signal Sep 16, 1997 Issued
Array ( [id] => 3965842 [patent_doc_number] => 05900743 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Programmable logic array devices with interconnect lines of various lengths' [patent_app_type] => 1 [patent_app_number] => 8/931251 [patent_app_country] => US [patent_app_date] => 1997-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4749 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/900/05900743.pdf [firstpage_image] =>[orig_patent_app_number] => 931251 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/931251
Programmable logic array devices with interconnect lines of various lengths Sep 15, 1997 Issued
Array ( [id] => 3965802 [patent_doc_number] => 05900741 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'CMOS buffer having stable threshold voltage' [patent_app_type] => 1 [patent_app_number] => 8/929209 [patent_app_country] => US [patent_app_date] => 1997-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4125 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/900/05900741.pdf [firstpage_image] =>[orig_patent_app_number] => 929209 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/929209
CMOS buffer having stable threshold voltage Sep 8, 1997 Issued
Array ( [id] => 4413367 [patent_doc_number] => 06172532 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Gate circuit and semiconductor circuit to process low amplitude signals, memory, processor and information processing system manufactured by use of them' [patent_app_type] => 1 [patent_app_number] => 8/925428 [patent_app_country] => US [patent_app_date] => 1997-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 36 [patent_no_of_words] => 18644 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 387 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/172/06172532.pdf [firstpage_image] =>[orig_patent_app_number] => 925428 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/925428
Gate circuit and semiconductor circuit to process low amplitude signals, memory, processor and information processing system manufactured by use of them Sep 7, 1997 Issued
Array ( [id] => 4077479 [patent_doc_number] => 06069492 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-30 [patent_title] => 'Voltage compensating CMOS input buffer circuit' [patent_app_type] => 1 [patent_app_number] => 8/925376 [patent_app_country] => US [patent_app_date] => 1997-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2359 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/069/06069492.pdf [firstpage_image] =>[orig_patent_app_number] => 925376 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/925376
Voltage compensating CMOS input buffer circuit Sep 7, 1997 Issued
Array ( [id] => 3982439 [patent_doc_number] => 05917343 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'MOS inverter circuit' [patent_app_type] => 1 [patent_app_number] => 8/922680 [patent_app_country] => US [patent_app_date] => 1997-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 2909 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/917/05917343.pdf [firstpage_image] =>[orig_patent_app_number] => 922680 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/922680
MOS inverter circuit Sep 2, 1997 Issued
Array ( [id] => 3803702 [patent_doc_number] => 05828228 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Null convention logic system' [patent_app_type] => 1 [patent_app_number] => 8/921568 [patent_app_country] => US [patent_app_date] => 1997-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 76 [patent_no_of_words] => 37733 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/828/05828228.pdf [firstpage_image] =>[orig_patent_app_number] => 921568 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/921568
Null convention logic system Sep 1, 1997 Issued
Array ( [id] => 4081947 [patent_doc_number] => 05966031 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-12 [patent_title] => 'Output circuit for integrated circuit devices' [patent_app_type] => 1 [patent_app_number] => 8/921192 [patent_app_country] => US [patent_app_date] => 1997-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11285 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/966/05966031.pdf [firstpage_image] =>[orig_patent_app_number] => 921192 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/921192
Output circuit for integrated circuit devices Aug 28, 1997 Issued
Array ( [id] => 4134437 [patent_doc_number] => 06127844 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'PCI-compatible programmable logic devices' [patent_app_type] => 1 [patent_app_number] => 8/919988 [patent_app_country] => US [patent_app_date] => 1997-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5168 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/127/06127844.pdf [firstpage_image] =>[orig_patent_app_number] => 919988 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/919988
PCI-compatible programmable logic devices Aug 27, 1997 Issued
Array ( [id] => 3955568 [patent_doc_number] => 05999016 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Architectures for programmable logic devices' [patent_app_type] => 1 [patent_app_number] => 8/920298 [patent_app_country] => US [patent_app_date] => 1997-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5888 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 390 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/999/05999016.pdf [firstpage_image] =>[orig_patent_app_number] => 920298 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/920298
Architectures for programmable logic devices Aug 27, 1997 Issued
Array ( [id] => 4303353 [patent_doc_number] => 06184710 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Programmable logic array devices with enhanced interconnectivity between adjacent logic regions' [patent_app_type] => 1 [patent_app_number] => 8/924768 [patent_app_country] => US [patent_app_date] => 1997-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4652 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/184/06184710.pdf [firstpage_image] =>[orig_patent_app_number] => 924768 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/924768
Programmable logic array devices with enhanced interconnectivity between adjacent logic regions Aug 26, 1997 Issued
Array ( [id] => 3956685 [patent_doc_number] => 05977789 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Fast-switching logic gate' [patent_app_type] => 1 [patent_app_number] => 8/918975 [patent_app_country] => US [patent_app_date] => 1997-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 5431 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/977/05977789.pdf [firstpage_image] =>[orig_patent_app_number] => 918975 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/918975
Fast-switching logic gate Aug 26, 1997 Issued
Array ( [id] => 3867591 [patent_doc_number] => 05796271 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-18 [patent_title] => 'Memory array having redundant word line' [patent_app_type] => 1 [patent_app_number] => 8/929347 [patent_app_country] => US [patent_app_date] => 1997-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 2942 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/796/05796271.pdf [firstpage_image] =>[orig_patent_app_number] => 929347 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/929347
Memory array having redundant word line Aug 25, 1997 Issued
Array ( [id] => 4019297 [patent_doc_number] => 05963047 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Noise supression using neighbor-sensing for a CMOS output buffer with a large DC current sink' [patent_app_type] => 1 [patent_app_number] => 8/917148 [patent_app_country] => US [patent_app_date] => 1997-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 6130 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/963/05963047.pdf [firstpage_image] =>[orig_patent_app_number] => 917148 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/917148
Noise supression using neighbor-sensing for a CMOS output buffer with a large DC current sink Aug 24, 1997 Issued
Array ( [id] => 3989182 [patent_doc_number] => 05861763 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-19 [patent_title] => 'Threshold voltage scalable buffer with reference level' [patent_app_type] => 1 [patent_app_number] => 8/918623 [patent_app_country] => US [patent_app_date] => 1997-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4311 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/861/05861763.pdf [firstpage_image] =>[orig_patent_app_number] => 918623 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/918623
Threshold voltage scalable buffer with reference level Aug 21, 1997 Issued
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