
Jon P. Santamauro
Examiner (ID: 474)
| Most Active Art Unit | 2819 |
| Art Unit(s) | 2819, 2509, 2878 |
| Total Applications | 622 |
| Issued Applications | 539 |
| Pending Applications | 28 |
| Abandoned Applications | 55 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4189181
[patent_doc_number] => 06020755
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-01
[patent_title] => 'Hybrid programmable gate arrays'
[patent_app_type] => 1
[patent_app_number] => 8/938550
[patent_app_country] => US
[patent_app_date] => 1997-09-26
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[pdf_file] => patents/06/020/06020755.pdf
[firstpage_image] =>[orig_patent_app_number] => 938550
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Array
(
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[patent_issue_date] => 1999-09-28
[patent_title] => 'Buffer for static in/static out dynamic speed'
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[patent_app_number] => 8/938131
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Array
(
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[patent_doc_number] => 05883524
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[patent_issue_date] => 1999-03-16
[patent_title] => 'Low overhead memory designs for IC terminals'
[patent_app_type] => 1
[patent_app_number] => 8/933896
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[patent_app_date] => 1997-09-19
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Array
(
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[patent_issue_date] => 1998-12-22
[patent_title] => 'System and method for testing integrated circuits connected together'
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Array
(
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[patent_issue_date] => 1999-08-10
[patent_title] => 'Three-input exclusive NOR circuit'
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Array
(
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[patent_issue_date] => 2000-03-28
[patent_title] => 'Output pad circuit using control signal'
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Array
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[patent_title] => 'Programmable logic array devices with interconnect lines of various lengths'
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[firstpage_image] =>[orig_patent_app_number] => 931251
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/931251 | Programmable logic array devices with interconnect lines of various lengths | Sep 15, 1997 | Issued |
Array
(
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[patent_doc_number] => 05900741
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[patent_title] => 'CMOS buffer having stable threshold voltage'
[patent_app_type] => 1
[patent_app_number] => 8/929209
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/929209 | CMOS buffer having stable threshold voltage | Sep 8, 1997 | Issued |
Array
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[id] => 4413367
[patent_doc_number] => 06172532
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-09
[patent_title] => 'Gate circuit and semiconductor circuit to process low amplitude signals, memory, processor and information processing system manufactured by use of them'
[patent_app_type] => 1
[patent_app_number] => 8/925428
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Array
(
[id] => 4077479
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[patent_issue_date] => 2000-05-30
[patent_title] => 'Voltage compensating CMOS input buffer circuit'
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Array
(
[id] => 3982439
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[patent_title] => 'MOS inverter circuit'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/922680 | MOS inverter circuit | Sep 2, 1997 | Issued |
Array
(
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Array
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[id] => 4081947
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Array
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Array
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Array
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Array
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Array
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