
Jon P. Santamauro
Examiner (ID: 474)
| Most Active Art Unit | 2819 |
| Art Unit(s) | 2819, 2509, 2878 |
| Total Applications | 622 |
| Issued Applications | 539 |
| Pending Applications | 28 |
| Abandoned Applications | 55 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3817773
[patent_doc_number] => 05811988
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-22
[patent_title] => 'PLA late signal circuitry using a specialized gap cell and PLA late signal circuitry using switched output'
[patent_app_type] => 1
[patent_app_number] => 8/915204
[patent_app_country] => US
[patent_app_date] => 1997-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 1971
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[pdf_file] => patents/05/811/05811988.pdf
[firstpage_image] =>[orig_patent_app_number] => 915204
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/915204 | PLA late signal circuitry using a specialized gap cell and PLA late signal circuitry using switched output | Aug 19, 1997 | Issued |
Array
(
[id] => 4072822
[patent_doc_number] => 06008670
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-28
[patent_title] => 'Differential CMOS logic family'
[patent_app_type] => 1
[patent_app_number] => 8/914195
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[patent_app_date] => 1997-08-19
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Array
(
[id] => 4110274
[patent_doc_number] => 06051991
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[patent_kind] => NA
[patent_issue_date] => 2000-04-18
[patent_title] => 'Architecture and interconnect scheme for programmable logic circuits'
[patent_app_type] => 1
[patent_app_number] => 8/909928
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[patent_app_date] => 1997-08-12
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Array
(
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[patent_issue_date] => 1999-11-16
[patent_title] => 'Method and apparatus for implementing a dynamic adiabatic logic family'
[patent_app_type] => 1
[patent_app_number] => 8/908582
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[patent_app_date] => 1997-08-08
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/908582 | Method and apparatus for implementing a dynamic adiabatic logic family | Aug 7, 1997 | Issued |
Array
(
[id] => 4199557
[patent_doc_number] => 06043678
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[patent_issue_date] => 2000-03-28
[patent_title] => 'Input circuit'
[patent_app_type] => 1
[patent_app_number] => 8/905497
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Array
(
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[patent_doc_number] => 06057708
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[patent_issue_date] => 2000-05-02
[patent_title] => 'Field programmable gate array having a dedicated internal bus system'
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[patent_app_number] => 8/902375
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/902375 | Field programmable gate array having a dedicated internal bus system | Jul 28, 1997 | Issued |
Array
(
[id] => 3956605
[patent_doc_number] => 05955897
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[patent_issue_date] => 1999-09-21
[patent_title] => 'Signal generation decoder circuit and method'
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[firstpage_image] =>[orig_patent_app_number] => 897773
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/897773 | Signal generation decoder circuit and method | Jul 20, 1997 | Issued |
Array
(
[id] => 4224416
[patent_doc_number] => 06111434
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[patent_kind] => NA
[patent_issue_date] => 2000-08-29
[patent_title] => 'Circuit having anti-charge share characteristics and method therefore'
[patent_app_type] => 1
[patent_app_number] => 8/897577
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[patent_app_date] => 1997-07-21
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[pdf_file] => patents/06/111/06111434.pdf
[firstpage_image] =>[orig_patent_app_number] => 897577
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/897577 | Circuit having anti-charge share characteristics and method therefore | Jul 20, 1997 | Issued |
Array
(
[id] => 4055726
[patent_doc_number] => 05869980
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[patent_kind] => NA
[patent_issue_date] => 1999-02-09
[patent_title] => 'Programming programmable transistor devices using state machines'
[patent_app_type] => 1
[patent_app_number] => 8/896146
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/896146 | Programming programmable transistor devices using state machines | Jul 16, 1997 | Issued |
Array
(
[id] => 4189245
[patent_doc_number] => 06020760
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[patent_kind] => NA
[patent_issue_date] => 2000-02-01
[patent_title] => 'I/O buffer circuit with pin multiplexing'
[patent_app_type] => 1
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[pdf_file] => patents/06/020/06020760.pdf
[firstpage_image] =>[orig_patent_app_number] => 895470
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/895470 | I/O buffer circuit with pin multiplexing | Jul 15, 1997 | Issued |
Array
(
[id] => 4112657
[patent_doc_number] => 06023174
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[patent_kind] => NA
[patent_issue_date] => 2000-02-08
[patent_title] => 'Adjustable, full CMOS input buffer for TTL, CMOS, or low swing input protocols'
[patent_app_type] => 1
[patent_app_number] => 8/891973
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[firstpage_image] =>[orig_patent_app_number] => 891973
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Array
(
[id] => 3767370
[patent_doc_number] => 05852371
[patent_country] => US
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[patent_issue_date] => 1998-12-22
[patent_title] => 'Low power, high speed level shifter'
[patent_app_type] => 1
[patent_app_number] => 8/890921
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/890921 | Low power, high speed level shifter | Jul 9, 1997 | Issued |
Array
(
[id] => 3934063
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[patent_title] => 'Fast wide decode in an FPGA using probe circuit'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/887380 | Fast wide decode in an FPGA using probe circuit | Jul 1, 1997 | Issued |
Array
(
[id] => 3956699
[patent_doc_number] => 05977790
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[patent_issue_date] => 1999-11-02
[patent_title] => 'Apparatus and method of providing a programmable slew rate control output driver'
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[firstpage_image] =>[orig_patent_app_number] => 884438
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/884438 | Apparatus and method of providing a programmable slew rate control output driver | Jun 26, 1997 | Issued |
Array
(
[id] => 3931242
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[patent_title] => 'Output circuit for conversion from CMOS circuit level to ECL circuit level'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/883874 | Output circuit for conversion from CMOS circuit level to ECL circuit level | Jun 26, 1997 | Issued |
Array
(
[id] => 4059054
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/879212 | High-voltage-tolerant output buffers in low-voltage technology | Jun 18, 1997 | Issued |
Array
(
[id] => 3839022
[patent_doc_number] => 05815008
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[patent_issue_date] => 1998-09-29
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/869547 | Resonant tunneling diode structures for funtionally complete low-power logic | Jun 4, 1997 | Issued |
Array
(
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Array
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/863876 | Circuitry for a low internal voltage integrated circuit | May 26, 1997 | Issued |