Search

Jon P. Santamauro

Examiner (ID: 474)

Most Active Art Unit
2819
Art Unit(s)
2819, 2509, 2878
Total Applications
622
Issued Applications
539
Pending Applications
28
Abandoned Applications
55

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3817773 [patent_doc_number] => 05811988 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-22 [patent_title] => 'PLA late signal circuitry using a specialized gap cell and PLA late signal circuitry using switched output' [patent_app_type] => 1 [patent_app_number] => 8/915204 [patent_app_country] => US [patent_app_date] => 1997-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1971 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/811/05811988.pdf [firstpage_image] =>[orig_patent_app_number] => 915204 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/915204
PLA late signal circuitry using a specialized gap cell and PLA late signal circuitry using switched output Aug 19, 1997 Issued
Array ( [id] => 4072822 [patent_doc_number] => 06008670 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Differential CMOS logic family' [patent_app_type] => 1 [patent_app_number] => 8/914195 [patent_app_country] => US [patent_app_date] => 1997-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 6278 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/008/06008670.pdf [firstpage_image] =>[orig_patent_app_number] => 914195 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/914195
Differential CMOS logic family Aug 18, 1997 Issued
Array ( [id] => 4110274 [patent_doc_number] => 06051991 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Architecture and interconnect scheme for programmable logic circuits' [patent_app_type] => 1 [patent_app_number] => 8/909928 [patent_app_country] => US [patent_app_date] => 1997-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 25 [patent_no_of_words] => 11534 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/051/06051991.pdf [firstpage_image] =>[orig_patent_app_number] => 909928 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/909928
Architecture and interconnect scheme for programmable logic circuits Aug 11, 1997 Issued
Array ( [id] => 4005286 [patent_doc_number] => 05986476 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Method and apparatus for implementing a dynamic adiabatic logic family' [patent_app_type] => 1 [patent_app_number] => 8/908582 [patent_app_country] => US [patent_app_date] => 1997-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5763 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/986/05986476.pdf [firstpage_image] =>[orig_patent_app_number] => 908582 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/908582
Method and apparatus for implementing a dynamic adiabatic logic family Aug 7, 1997 Issued
Array ( [id] => 4199557 [patent_doc_number] => 06043678 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'Input circuit' [patent_app_type] => 1 [patent_app_number] => 8/905497 [patent_app_country] => US [patent_app_date] => 1997-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 8804 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/043/06043678.pdf [firstpage_image] =>[orig_patent_app_number] => 905497 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/905497
Input circuit Aug 3, 1997 Issued
Array ( [id] => 4115205 [patent_doc_number] => 06057708 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Field programmable gate array having a dedicated internal bus system' [patent_app_type] => 1 [patent_app_number] => 8/902375 [patent_app_country] => US [patent_app_date] => 1997-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2213 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/057/06057708.pdf [firstpage_image] =>[orig_patent_app_number] => 902375 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/902375
Field programmable gate array having a dedicated internal bus system Jul 28, 1997 Issued
Array ( [id] => 3956605 [patent_doc_number] => 05955897 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Signal generation decoder circuit and method' [patent_app_type] => 1 [patent_app_number] => 8/897773 [patent_app_country] => US [patent_app_date] => 1997-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3390 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/955/05955897.pdf [firstpage_image] =>[orig_patent_app_number] => 897773 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/897773
Signal generation decoder circuit and method Jul 20, 1997 Issued
Array ( [id] => 4224416 [patent_doc_number] => 06111434 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Circuit having anti-charge share characteristics and method therefore' [patent_app_type] => 1 [patent_app_number] => 8/897577 [patent_app_country] => US [patent_app_date] => 1997-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 7452 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/111/06111434.pdf [firstpage_image] =>[orig_patent_app_number] => 897577 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/897577
Circuit having anti-charge share characteristics and method therefore Jul 20, 1997 Issued
Array ( [id] => 4055726 [patent_doc_number] => 05869980 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-09 [patent_title] => 'Programming programmable transistor devices using state machines' [patent_app_type] => 1 [patent_app_number] => 8/896146 [patent_app_country] => US [patent_app_date] => 1997-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 5867 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/869/05869980.pdf [firstpage_image] =>[orig_patent_app_number] => 896146 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/896146
Programming programmable transistor devices using state machines Jul 16, 1997 Issued
Array ( [id] => 4189245 [patent_doc_number] => 06020760 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'I/O buffer circuit with pin multiplexing' [patent_app_type] => 1 [patent_app_number] => 8/895470 [patent_app_country] => US [patent_app_date] => 1997-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6923 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/020/06020760.pdf [firstpage_image] =>[orig_patent_app_number] => 895470 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/895470
I/O buffer circuit with pin multiplexing Jul 15, 1997 Issued
Array ( [id] => 4112657 [patent_doc_number] => 06023174 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-08 [patent_title] => 'Adjustable, full CMOS input buffer for TTL, CMOS, or low swing input protocols' [patent_app_type] => 1 [patent_app_number] => 8/891973 [patent_app_country] => US [patent_app_date] => 1997-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 7384 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 334 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/023/06023174.pdf [firstpage_image] =>[orig_patent_app_number] => 891973 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/891973
Adjustable, full CMOS input buffer for TTL, CMOS, or low swing input protocols Jul 10, 1997 Issued
Array ( [id] => 3767370 [patent_doc_number] => 05852371 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-22 [patent_title] => 'Low power, high speed level shifter' [patent_app_type] => 1 [patent_app_number] => 8/890921 [patent_app_country] => US [patent_app_date] => 1997-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 2796 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/852/05852371.pdf [firstpage_image] =>[orig_patent_app_number] => 890921 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/890921
Low power, high speed level shifter Jul 9, 1997 Issued
Array ( [id] => 3934063 [patent_doc_number] => 05952852 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Fast wide decode in an FPGA using probe circuit' [patent_app_type] => 1 [patent_app_number] => 8/887380 [patent_app_country] => US [patent_app_date] => 1997-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 5348 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/952/05952852.pdf [firstpage_image] =>[orig_patent_app_number] => 887380 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/887380
Fast wide decode in an FPGA using probe circuit Jul 1, 1997 Issued
Array ( [id] => 3956699 [patent_doc_number] => 05977790 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Apparatus and method of providing a programmable slew rate control output driver' [patent_app_type] => 1 [patent_app_number] => 8/884438 [patent_app_country] => US [patent_app_date] => 1997-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2355 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/977/05977790.pdf [firstpage_image] =>[orig_patent_app_number] => 884438 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/884438
Apparatus and method of providing a programmable slew rate control output driver Jun 26, 1997 Issued
Array ( [id] => 3931242 [patent_doc_number] => 05945842 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Output circuit for conversion from CMOS circuit level to ECL circuit level' [patent_app_type] => 1 [patent_app_number] => 8/883874 [patent_app_country] => US [patent_app_date] => 1997-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4406 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/945/05945842.pdf [firstpage_image] =>[orig_patent_app_number] => 883874 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/883874
Output circuit for conversion from CMOS circuit level to ECL circuit level Jun 26, 1997 Issued
Array ( [id] => 4059054 [patent_doc_number] => 05933027 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'High-voltage-tolerant output buffers in low-voltage technology' [patent_app_type] => 1 [patent_app_number] => 8/879212 [patent_app_country] => US [patent_app_date] => 1997-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2524 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/933/05933027.pdf [firstpage_image] =>[orig_patent_app_number] => 879212 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/879212
High-voltage-tolerant output buffers in low-voltage technology Jun 18, 1997 Issued
Array ( [id] => 3839022 [patent_doc_number] => 05815008 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-29 [patent_title] => 'Resonant tunneling diode structures for funtionally complete low-power logic' [patent_app_type] => 1 [patent_app_number] => 8/869547 [patent_app_country] => US [patent_app_date] => 1997-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 7214 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/815/05815008.pdf [firstpage_image] =>[orig_patent_app_number] => 869547 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/869547
Resonant tunneling diode structures for funtionally complete low-power logic Jun 4, 1997 Issued
Array ( [id] => 3946312 [patent_doc_number] => 05973507 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Exclusive-or gate for use in delay using transmission gate circuitry' [patent_app_type] => 1 [patent_app_number] => 8/869004 [patent_app_country] => US [patent_app_date] => 1997-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7606 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/973/05973507.pdf [firstpage_image] =>[orig_patent_app_number] => 869004 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/869004
Exclusive-or gate for use in delay using transmission gate circuitry Jun 3, 1997 Issued
Array ( [id] => 4211684 [patent_doc_number] => 06078195 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Logic blocks with mixed low and regular V.sub.t MOSFET devices for VLSI design in the deep sub-micron regime' [patent_app_type] => 1 [patent_app_number] => 8/868231 [patent_app_country] => US [patent_app_date] => 1997-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 6715 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/078/06078195.pdf [firstpage_image] =>[orig_patent_app_number] => 868231 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/868231
Logic blocks with mixed low and regular V.sub.t MOSFET devices for VLSI design in the deep sub-micron regime Jun 2, 1997 Issued
Array ( [id] => 4092431 [patent_doc_number] => 06025737 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Circuitry for a low internal voltage integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/863876 [patent_app_country] => US [patent_app_date] => 1997-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 34 [patent_no_of_words] => 15794 [patent_no_of_claims] => 129 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/025/06025737.pdf [firstpage_image] =>[orig_patent_app_number] => 863876 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/863876
Circuitry for a low internal voltage integrated circuit May 26, 1997 Issued
Menu