Jon P. Santamauro

Array ( [id] => 4139456 [patent_doc_number] => 06147511 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Overvoltage-tolerant interface for integrated circuits' [patent_app_type] => 1 [patent_app_number] => 8/863886 [patent_app_country] => US [patent_app_date] => 1997-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 34 [patent_no_of_words] => 15757 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/147/06147511.pdf [firstpage_image] =>[orig_patent_app_number] => 863886 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4058278 [patent_doc_number] => 05969542 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'High speed gate oxide protected level shifter' [patent_app_type] => 1 [patent_app_number] => 8/861038 [patent_app_country] => US [patent_app_date] => 1997-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3951 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 431 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/969/05969542.pdf [firstpage_image] =>[orig_patent_app_number] => 861038 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3946324 [patent_doc_number] => 05973508 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Voltage translation circuit for mixed voltage applications' [patent_app_type] => 1 [patent_app_number] => 8/859934 [patent_app_country] => US [patent_app_date] => 1997-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 6841 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/973/05973508.pdf [firstpage_image] =>[orig_patent_app_number] => 859934 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4366816 [patent_doc_number] => 06191608 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Techniques for programming programmable logic array devices' [patent_app_type] => 1 [patent_app_number] => 8/851250 [patent_app_country] => US [patent_app_date] => 1997-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 6045 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/191/06191608.pdf [firstpage_image] =>[orig_patent_app_number] => 851250 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4011621 [patent_doc_number] => 06005416 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-21 [patent_title] => 'Compiled self-resetting CMOS logic array macros' [patent_app_type] => 1 [patent_app_number] => 8/850190 [patent_app_country] => US [patent_app_date] => 1997-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 9139 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/005/06005416.pdf [firstpage_image] =>[orig_patent_app_number] => 850190 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3822404 [patent_doc_number] => 05770951 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-23 [patent_title] => 'Configuration logic to eliminate signal contention during reconfiguration' [patent_app_type] => 1 [patent_app_number] => 8/847326 [patent_app_country] => US [patent_app_date] => 1997-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1938 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/770/05770951.pdf [firstpage_image] =>[orig_patent_app_number] => 847326 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3814439 [patent_doc_number] => 05831449 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-03 [patent_title] => 'Output circuit for use in a semiconductor integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/844663 [patent_app_country] => US [patent_app_date] => 1997-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 56 [patent_no_of_words] => 11136 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/831/05831449.pdf [firstpage_image] =>[orig_patent_app_number] => 844663 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3796460 [patent_doc_number] => 05841300 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-24 [patent_title] => 'Semiconductor integrated circuit apparatus' [patent_app_type] => 1 [patent_app_number] => 8/838193 [patent_app_country] => US [patent_app_date] => 1997-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 34 [patent_no_of_words] => 8237 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/841/05841300.pdf [firstpage_image] =>[orig_patent_app_number] => 838193 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3934548 [patent_doc_number] => 05877633 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-02 [patent_title] => 'Bidirectional voltage translator' [patent_app_type] => 1 [patent_app_number] => 8/839732 [patent_app_country] => US [patent_app_date] => 1997-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4602 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/877/05877633.pdf [firstpage_image] =>[orig_patent_app_number] => 839732 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3956710 [patent_doc_number] => 05977791 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Embedded memory block with FIFO mode for programmable logic device' [patent_app_type] => 1 [patent_app_number] => 8/834426 [patent_app_country] => US [patent_app_date] => 1997-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5320 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/977/05977791.pdf [firstpage_image] =>[orig_patent_app_number] => 834426 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4021218 [patent_doc_number] => 05880595 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'IC having memoried terminals and zero-delay boundary scan' [patent_app_type] => 1 [patent_app_number] => 8/827844 [patent_app_country] => US [patent_app_date] => 1997-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 47 [patent_no_of_words] => 10576 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/880/05880595.pdf [firstpage_image] =>[orig_patent_app_number] => 827844 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3776762 [patent_doc_number] => 05850151 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-15 [patent_title] => 'Programmable logic array intergrated circuit devices' [patent_app_type] => 1 [patent_app_number] => 8/834996 [patent_app_country] => US [patent_app_date] => 1997-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12869 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/850/05850151.pdf [firstpage_image] =>[orig_patent_app_number] => 834996 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3776779 [patent_doc_number] => 05850152 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-15 [patent_title] => 'Programmable logic array integrated circuit devices' [patent_app_type] => 1 [patent_app_number] => 8/834998 [patent_app_country] => US [patent_app_date] => 1997-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12863 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/850/05850152.pdf [firstpage_image] =>[orig_patent_app_number] => 834998 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4199530 [patent_doc_number] => 06043676 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'Wide exclusive or and wide-input and for PLDS' [patent_app_type] => 1 [patent_app_number] => 8/825821 [patent_app_country] => US [patent_app_date] => 1997-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6480 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/043/06043676.pdf [firstpage_image] =>[orig_patent_app_number] => 825821 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3963159 [patent_doc_number] => 05936429 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Interface circuit and method for transmitting binary logic signals with reduced power dissipation' [patent_app_type] => 1 [patent_app_number] => 8/825464 [patent_app_country] => US [patent_app_date] => 1997-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 8019 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/936/05936429.pdf [firstpage_image] =>[orig_patent_app_number] => 825464 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3767298 [patent_doc_number] => 05852366 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-22 [patent_title] => 'High voltage level shift circuit including CMOS transistor having thin gate insulating film' [patent_app_type] => 1 [patent_app_number] => 8/824434 [patent_app_country] => US [patent_app_date] => 1997-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4186 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/852/05852366.pdf [firstpage_image] =>[orig_patent_app_number] => 824434 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4004537 [patent_doc_number] => 05923186 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Two state bi-directional bus' [patent_app_type] => 1 [patent_app_number] => 8/823032 [patent_app_country] => US [patent_app_date] => 1997-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 6949 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/923/05923186.pdf [firstpage_image] =>[orig_patent_app_number] => 823032 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4050233 [patent_doc_number] => 05909128 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-01 [patent_title] => 'FETs logic circuit' [patent_app_type] => 1 [patent_app_number] => 8/823039 [patent_app_country] => US [patent_app_date] => 1997-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5966 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/909/05909128.pdf [firstpage_image] =>[orig_patent_app_number] => 823039 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4028902 [patent_doc_number] => 05926039 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Active load for an N channel logic network' [patent_app_type] => 1 [patent_app_number] => 8/820728 [patent_app_country] => US [patent_app_date] => 1997-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2056 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926039.pdf [firstpage_image] =>[orig_patent_app_number] => 820728 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3950288 [patent_doc_number] => 05982198 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Free inverter circuit' [patent_app_type] => 1 [patent_app_number] => 8/820928 [patent_app_country] => US [patent_app_date] => 1997-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 19 [patent_no_of_words] => 2519 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/982/05982198.pdf [firstpage_image] =>[orig_patent_app_number] => 820928 [rel_patent_id] =>[rel_patent_doc_number] =>)