
Jon P. Santamauro
Examiner (ID: 474)
| Most Active Art Unit | 2819 |
| Art Unit(s) | 2819, 2509, 2878 |
| Total Applications | 622 |
| Issued Applications | 539 |
| Pending Applications | 28 |
| Abandoned Applications | 55 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4028918
[patent_doc_number] => 05926040
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-20
[patent_title] => 'Logic circuit'
[patent_app_type] => 1
[patent_app_number] => 8/819394
[patent_app_country] => US
[patent_app_date] => 1997-03-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 23
[patent_no_of_words] => 10716
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 378
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/926/05926040.pdf
[firstpage_image] =>[orig_patent_app_number] => 819394
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/819394 | Logic circuit | Mar 16, 1997 | Issued |
Array
(
[id] => 3934004
[patent_doc_number] => 05952848
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-14
[patent_title] => 'High-voltage tolerant input buffer in low-voltage technology'
[patent_app_type] => 1
[patent_app_number] => 8/818844
[patent_app_country] => US
[patent_app_date] => 1997-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 2071
[patent_no_of_claims] => 22
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[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/952/05952848.pdf
[firstpage_image] =>[orig_patent_app_number] => 818844
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/818844 | High-voltage tolerant input buffer in low-voltage technology | Mar 13, 1997 | Issued |
Array
(
[id] => 3782299
[patent_doc_number] => 05808482
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-15
[patent_title] => 'Row decoder with level translator'
[patent_app_type] => 1
[patent_app_number] => 8/816860
[patent_app_country] => US
[patent_app_date] => 1997-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 2899
[patent_no_of_claims] => 43
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/808/05808482.pdf
[firstpage_image] =>[orig_patent_app_number] => 816860
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/816860 | Row decoder with level translator | Mar 12, 1997 | Issued |
Array
(
[id] => 3928322
[patent_doc_number] => 05914618
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-22
[patent_title] => 'Optimum noise isolated I/O with minimized footprint'
[patent_app_type] => 1
[patent_app_number] => 8/814875
[patent_app_country] => US
[patent_app_date] => 1997-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 9336
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 404
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/914/05914618.pdf
[firstpage_image] =>[orig_patent_app_number] => 814875
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/814875 | Optimum noise isolated I/O with minimized footprint | Mar 10, 1997 | Issued |
Array
(
[id] => 4033482
[patent_doc_number] => 05903166
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-05-11
[patent_title] => 'Circuit for immunizing an integrated circuit from noise affecting enable signals of the integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 8/811548
[patent_app_country] => US
[patent_app_date] => 1997-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 3973
[patent_no_of_claims] => 27
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[pdf_file] => patents/05/903/05903166.pdf
[firstpage_image] =>[orig_patent_app_number] => 811548
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/811548 | Circuit for immunizing an integrated circuit from noise affecting enable signals of the integrated circuit | Mar 3, 1997 | Issued |
Array
(
[id] => 3782249
[patent_doc_number] => 05808478
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-15
[patent_title] => 'Digitally controlled output buffer to incrementally match line impedance and maintain slew rate independent of capacitive output loading'
[patent_app_type] => 1
[patent_app_number] => 8/804020
[patent_app_country] => US
[patent_app_date] => 1997-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 4835
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/808/05808478.pdf
[firstpage_image] =>[orig_patent_app_number] => 804020
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/804020 | Digitally controlled output buffer to incrementally match line impedance and maintain slew rate independent of capacitive output loading | Feb 20, 1997 | Issued |
Array
(
[id] => 3991129
[patent_doc_number] => 05910734
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-08
[patent_title] => 'Voltage level translator'
[patent_app_type] => 1
[patent_app_number] => 8/803343
[patent_app_country] => US
[patent_app_date] => 1997-02-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/05/910/05910734.pdf
[firstpage_image] =>[orig_patent_app_number] => 803343
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/803343 | Voltage level translator | Feb 19, 1997 | Issued |
Array
(
[id] => 3982453
[patent_doc_number] => 05917344
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-29
[patent_title] => 'Driver circuit'
[patent_app_type] => 1
[patent_app_number] => 8/799846
[patent_app_country] => US
[patent_app_date] => 1997-02-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 2238
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 216
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/917/05917344.pdf
[firstpage_image] =>[orig_patent_app_number] => 799846
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/799846 | Driver circuit | Feb 12, 1997 | Issued |
Array
(
[id] => 4040434
[patent_doc_number] => 05994917
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-30
[patent_title] => 'Method and apparatus for sequencing an integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 8/796430
[patent_app_country] => US
[patent_app_date] => 1997-02-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
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[patent_no_of_words] => 1497
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[pdf_file] => patents/05/994/05994917.pdf
[firstpage_image] =>[orig_patent_app_number] => 796430
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/796430 | Method and apparatus for sequencing an integrated circuit | Feb 9, 1997 | Issued |
Array
(
[id] => 3882120
[patent_doc_number] => 05825198
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-20
[patent_title] => 'Semiconductor integrated circuits with power reduction mechanism'
[patent_app_type] => 1
[patent_app_number] => 8/797051
[patent_app_country] => US
[patent_app_date] => 1997-02-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
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[patent_no_of_words] => 15398
[patent_no_of_claims] => 19
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/825/05825198.pdf
[firstpage_image] =>[orig_patent_app_number] => 797051
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/797051 | Semiconductor integrated circuits with power reduction mechanism | Feb 9, 1997 | Issued |
Array
(
[id] => 4049905
[patent_doc_number] => 05874833
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-23
[patent_title] => 'True/complement output bus for reduced simulataneous switching noise'
[patent_app_type] => 1
[patent_app_number] => 8/794041
[patent_app_country] => US
[patent_app_date] => 1997-02-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/874/05874833.pdf
[firstpage_image] =>[orig_patent_app_number] => 794041
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/794041 | True/complement output bus for reduced simulataneous switching noise | Feb 2, 1997 | Issued |
| 08/790127 | IC HAVING MEMORIED TERMINALS AND ZERO-DELAY BOUNDARY SCAN | Jan 28, 1997 | Abandoned |
Array
(
[id] => 3881460
[patent_doc_number] => 05764081
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-09
[patent_title] => 'Null convention interface circuits'
[patent_app_type] => 1
[patent_app_number] => 8/788914
[patent_app_country] => US
[patent_app_date] => 1997-01-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
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[patent_no_of_words] => 5812
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[pdf_file] => patents/05/764/05764081.pdf
[firstpage_image] =>[orig_patent_app_number] => 788914
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/788914 | Null convention interface circuits | Jan 21, 1997 | Issued |
Array
(
[id] => 3847522
[patent_doc_number] => 05744981
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-28
[patent_title] => 'Programmable logic cell with input polarity control'
[patent_app_type] => 1
[patent_app_number] => 8/784225
[patent_app_country] => US
[patent_app_date] => 1997-01-16
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/744/05744981.pdf
[firstpage_image] =>[orig_patent_app_number] => 784225
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/784225 | Programmable logic cell with input polarity control | Jan 15, 1997 | Issued |
Array
(
[id] => 3782262
[patent_doc_number] => 05808479
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-15
[patent_title] => 'High speed programmable logic architecture'
[patent_app_type] => 1
[patent_app_number] => 8/783809
[patent_app_country] => US
[patent_app_date] => 1997-01-16
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/808/05808479.pdf
[firstpage_image] =>[orig_patent_app_number] => 783809
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/783809 | High speed programmable logic architecture | Jan 15, 1997 | Issued |
Array
(
[id] => 3814494
[patent_doc_number] => 05831453
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-03
[patent_title] => 'Method and apparatus for low power data transmission'
[patent_app_type] => 1
[patent_app_number] => 8/777547
[patent_app_country] => US
[patent_app_date] => 1996-12-30
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[pdf_file] => patents/05/831/05831453.pdf
[firstpage_image] =>[orig_patent_app_number] => 777547
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/777547 | Method and apparatus for low power data transmission | Dec 29, 1996 | Issued |
Array
(
[id] => 4092490
[patent_doc_number] => 06025741
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-15
[patent_title] => 'Conditional restore for execution unit'
[patent_app_type] => 1
[patent_app_number] => 8/772643
[patent_app_country] => US
[patent_app_date] => 1996-12-23
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[pdf_file] => patents/06/025/06025741.pdf
[firstpage_image] =>[orig_patent_app_number] => 772643
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/772643 | Conditional restore for execution unit | Dec 22, 1996 | Issued |
Array
(
[id] => 4104003
[patent_doc_number] => 06097218
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-01
[patent_title] => 'Method and device for isolating noise sensitive circuitry from switching current noise on semiconductor substrate'
[patent_app_type] => 1
[patent_app_number] => 8/777686
[patent_app_country] => US
[patent_app_date] => 1996-12-20
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[pdf_file] => patents/06/097/06097218.pdf
[firstpage_image] =>[orig_patent_app_number] => 777686
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/777686 | Method and device for isolating noise sensitive circuitry from switching current noise on semiconductor substrate | Dec 19, 1996 | Issued |
Array
(
[id] => 3887073
[patent_doc_number] => 05798659
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[patent_issue_date] => 1998-08-25
[patent_title] => 'Supply and interface configurable input/output buffer'
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[pdf_file] => patents/05/798/05798659.pdf
[firstpage_image] =>[orig_patent_app_number] => 766572
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/766572 | Supply and interface configurable input/output buffer | Dec 11, 1996 | Issued |
Array
(
[id] => 3730898
[patent_doc_number] => 05701095
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[patent_kind] => NA
[patent_issue_date] => 1997-12-23
[patent_title] => 'High speed, low noise CMOS multiplexer with precharge'
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[patent_app_date] => 1996-12-10
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[pdf_file] => patents/05/701/05701095.pdf
[firstpage_image] =>[orig_patent_app_number] => 763036
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/763036 | High speed, low noise CMOS multiplexer with precharge | Dec 9, 1996 | Issued |