
Jon P. Santamauro
Examiner (ID: 474)
| Most Active Art Unit | 2819 |
| Art Unit(s) | 2819, 2509, 2878 |
| Total Applications | 622 |
| Issued Applications | 539 |
| Pending Applications | 28 |
| Abandoned Applications | 55 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3734230
[patent_doc_number] => 05670894
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-23
[patent_title] => 'Semiconductor device having output signal control circuit'
[patent_app_type] => 1
[patent_app_number] => 8/754029
[patent_app_country] => US
[patent_app_date] => 1996-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 48
[patent_no_of_words] => 6873
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 193
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/670/05670894.pdf
[firstpage_image] =>[orig_patent_app_number] => 754029
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/754029 | Semiconductor device having output signal control circuit | Dec 3, 1996 | Issued |
Array
(
[id] => 4186463
[patent_doc_number] => 06037799
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-14
[patent_title] => 'Circuit and method for selecting a signal'
[patent_app_type] => 1
[patent_app_number] => 8/758587
[patent_app_country] => US
[patent_app_date] => 1996-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 16
[patent_no_of_words] => 10784
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/037/06037799.pdf
[firstpage_image] =>[orig_patent_app_number] => 758587
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/758587 | Circuit and method for selecting a signal | Nov 26, 1996 | Issued |
Array
(
[id] => 4182140
[patent_doc_number] => 06084431
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-04
[patent_title] => 'Output circuit providing protection against external voltages in excess of power-supply voltage'
[patent_app_type] => 1
[patent_app_number] => 8/757562
[patent_app_country] => US
[patent_app_date] => 1996-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 14
[patent_no_of_words] => 9927
[patent_no_of_claims] => 38
[patent_no_of_ind_claims] => 14
[patent_words_short_claim] => 226
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/084/06084431.pdf
[firstpage_image] =>[orig_patent_app_number] => 757562
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/757562 | Output circuit providing protection against external voltages in excess of power-supply voltage | Nov 26, 1996 | Issued |
Array
(
[id] => 4021392
[patent_doc_number] => 05880606
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-09
[patent_title] => 'Programmable driver circuit for multi-source buses'
[patent_app_type] => 1
[patent_app_number] => 8/757061
[patent_app_country] => US
[patent_app_date] => 1996-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 3327
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/880/05880606.pdf
[firstpage_image] =>[orig_patent_app_number] => 757061
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/757061 | Programmable driver circuit for multi-source buses | Nov 25, 1996 | Issued |
Array
(
[id] => 3986924
[patent_doc_number] => 05949252
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-07
[patent_title] => 'Bus configuration and input/output buffer'
[patent_app_type] => 1
[patent_app_number] => 8/754760
[patent_app_country] => US
[patent_app_date] => 1996-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 33
[patent_no_of_words] => 10935
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/949/05949252.pdf
[firstpage_image] =>[orig_patent_app_number] => 754760
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/754760 | Bus configuration and input/output buffer | Nov 20, 1996 | Issued |
Array
(
[id] => 3812928
[patent_doc_number] => 05854560
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-29
[patent_title] => 'CMOS output buffer having a high current driving capability with low noise'
[patent_app_type] => 1
[patent_app_number] => 8/749360
[patent_app_country] => US
[patent_app_date] => 1996-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 5934
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 228
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/854/05854560.pdf
[firstpage_image] =>[orig_patent_app_number] => 749360
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/749360 | CMOS output buffer having a high current driving capability with low noise | Nov 19, 1996 | Issued |
Array
(
[id] => 3746865
[patent_doc_number] => 05754060
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-19
[patent_title] => 'Electronic system including high performance backplane driver/receiver circuits'
[patent_app_type] => 1
[patent_app_number] => 8/747789
[patent_app_country] => US
[patent_app_date] => 1996-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 4736
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/754/05754060.pdf
[firstpage_image] =>[orig_patent_app_number] => 747789
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/747789 | Electronic system including high performance backplane driver/receiver circuits | Nov 13, 1996 | Issued |
Array
(
[id] => 3784478
[patent_doc_number] => 05818257
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-06
[patent_title] => 'CMOS interface for coupling a low voltage integrated circuit with devices powered at a higher supply voltage'
[patent_app_type] => 1
[patent_app_number] => 8/749971
[patent_app_country] => US
[patent_app_date] => 1996-11-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 4278
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 358
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/818/05818257.pdf
[firstpage_image] =>[orig_patent_app_number] => 749971
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/749971 | CMOS interface for coupling a low voltage integrated circuit with devices powered at a higher supply voltage | Nov 13, 1996 | Issued |
Array
(
[id] => 3801299
[patent_doc_number] => 05781033
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-14
[patent_title] => 'Logic module with configurable combinational and sequential blocks'
[patent_app_type] => 1
[patent_app_number] => 8/754188
[patent_app_country] => US
[patent_app_date] => 1996-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 3027
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/781/05781033.pdf
[firstpage_image] =>[orig_patent_app_number] => 754188
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/754188 | Logic module with configurable combinational and sequential blocks | Nov 11, 1996 | Issued |
Array
(
[id] => 3847212
[patent_doc_number] => 05847577
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-08
[patent_title] => 'DRAM memory cell for programmable logic devices'
[patent_app_type] => 1
[patent_app_number] => 8/758286
[patent_app_country] => US
[patent_app_date] => 1996-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 4229
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/847/05847577.pdf
[firstpage_image] =>[orig_patent_app_number] => 758286
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/758286 | DRAM memory cell for programmable logic devices | Oct 31, 1996 | Issued |
Array
(
[id] => 4028789
[patent_doc_number] => 05926031
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-20
[patent_title] => 'High speed digital bus termination'
[patent_app_type] => 1
[patent_app_number] => 8/739372
[patent_app_country] => US
[patent_app_date] => 1996-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3043
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/926/05926031.pdf
[firstpage_image] =>[orig_patent_app_number] => 739372
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/739372 | High speed digital bus termination | Oct 28, 1996 | Issued |
Array
(
[id] => 4081877
[patent_doc_number] => 05966026
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-12
[patent_title] => 'Output buffer with improved tolerance to overvoltage'
[patent_app_type] => 1
[patent_app_number] => 8/738598
[patent_app_country] => US
[patent_app_date] => 1996-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 8596
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 11
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/966/05966026.pdf
[firstpage_image] =>[orig_patent_app_number] => 738598
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/738598 | Output buffer with improved tolerance to overvoltage | Oct 28, 1996 | Issued |
Array
(
[id] => 3747316
[patent_doc_number] => 05786709
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-28
[patent_title] => 'Integrated circuit output driver incorporating power distribution noise suppression circuitry'
[patent_app_type] => 1
[patent_app_number] => 8/738214
[patent_app_country] => US
[patent_app_date] => 1996-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 4387
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 186
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/786/05786709.pdf
[firstpage_image] =>[orig_patent_app_number] => 738214
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/738214 | Integrated circuit output driver incorporating power distribution noise suppression circuitry | Oct 24, 1996 | Issued |
Array
(
[id] => 4071554
[patent_doc_number] => 05867037
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-02
[patent_title] => 'Method and apparatus of programming FPGA devices through ASIC devices'
[patent_app_type] => 1
[patent_app_number] => 8/736303
[patent_app_country] => US
[patent_app_date] => 1996-10-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 1928
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/867/05867037.pdf
[firstpage_image] =>[orig_patent_app_number] => 736303
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/736303 | Method and apparatus of programming FPGA devices through ASIC devices | Oct 23, 1996 | Issued |
Array
(
[id] => 3991153
[patent_doc_number] => 05910736
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-08
[patent_title] => 'Differential-type data transmitter'
[patent_app_type] => 1
[patent_app_number] => 8/733636
[patent_app_country] => US
[patent_app_date] => 1996-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 10884
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/910/05910736.pdf
[firstpage_image] =>[orig_patent_app_number] => 733636
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/733636 | Differential-type data transmitter | Oct 16, 1996 | Issued |
Array
(
[id] => 3887062
[patent_doc_number] => 05798658
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-25
[patent_title] => 'Source-coupled logic with reference controlled inputs'
[patent_app_type] => 1
[patent_app_number] => 8/732209
[patent_app_country] => US
[patent_app_date] => 1996-10-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 14
[patent_no_of_words] => 5923
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 38
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/798/05798658.pdf
[firstpage_image] =>[orig_patent_app_number] => 732209
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/732209 | Source-coupled logic with reference controlled inputs | Oct 15, 1996 | Issued |
Array
(
[id] => 4063404
[patent_doc_number] => 05864245
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-01-26
[patent_title] => 'Output circuit with overvoltage protection'
[patent_app_type] => 1
[patent_app_number] => 8/730603
[patent_app_country] => US
[patent_app_date] => 1996-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 3225
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/864/05864245.pdf
[firstpage_image] =>[orig_patent_app_number] => 730603
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/730603 | Output circuit with overvoltage protection | Oct 14, 1996 | Issued |
Array
(
[id] => 3737353
[patent_doc_number] => 05666067
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-09
[patent_title] => 'Voltage compensating CMOS input buffer circuit'
[patent_app_type] => 1
[patent_app_number] => 8/731148
[patent_app_country] => US
[patent_app_date] => 1996-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 2359
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/666/05666067.pdf
[firstpage_image] =>[orig_patent_app_number] => 731148
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/731148 | Voltage compensating CMOS input buffer circuit | Oct 9, 1996 | Issued |
Array
(
[id] => 3989145
[patent_doc_number] => 05861761
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-01-19
[patent_title] => 'Hierarchically connectable configurable cellular array'
[patent_app_type] => 1
[patent_app_number] => 8/725173
[patent_app_country] => US
[patent_app_date] => 1996-10-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 41
[patent_figures_cnt] => 61
[patent_no_of_words] => 27746
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/861/05861761.pdf
[firstpage_image] =>[orig_patent_app_number] => 725173
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/725173 | Hierarchically connectable configurable cellular array | Oct 2, 1996 | Issued |
Array
(
[id] => 3867534
[patent_doc_number] => 05796268
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-18
[patent_title] => 'Programmable logic device with partial switch matrix and bypass mechanism'
[patent_app_type] => 1
[patent_app_number] => 8/723615
[patent_app_country] => US
[patent_app_date] => 1996-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 16
[patent_no_of_words] => 6467
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/796/05796268.pdf
[firstpage_image] =>[orig_patent_app_number] => 723615
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/723615 | Programmable logic device with partial switch matrix and bypass mechanism | Oct 1, 1996 | Issued |