Search

Jonathan Bradford

Examiner (ID: 11567, Phone: (571)270-5199 , Office: P/3744 )

Most Active Art Unit
3763
Art Unit(s)
3763, 4176, 3744
Total Applications
1374
Issued Applications
1024
Pending Applications
89
Abandoned Applications
296

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17084099 [patent_doc_number] => 20210279105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => FIELD SPECIALIZATION TO REDUCE MEMORY-ACCESS STALLS AND ALLOCATION REQUESTS IN DATA-INTENSIVE APPLICATIONS [patent_app_type] => utility [patent_app_number] => 16/620769 [patent_app_country] => US [patent_app_date] => 2018-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4994 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16620769 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/620769
Field specialization to reduce memory-access stalls and allocation requests in data-intensive applications Jun 21, 2018 Issued
Array ( [id] => 16574121 [patent_doc_number] => 10896044 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-19 [patent_title] => Low latency synchronization for operation cache and instruction cache fetching and decoding instructions [patent_app_type] => utility [patent_app_number] => 16/014715 [patent_app_country] => US [patent_app_date] => 2018-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9850 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 293 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16014715 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/014715
Low latency synchronization for operation cache and instruction cache fetching and decoding instructions Jun 20, 2018 Issued
Array ( [id] => 13787981 [patent_doc_number] => 20190007529 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-03 [patent_title] => METHODS AND SYSTEMS FOR AUTONOMOUS MEMORY [patent_app_type] => utility [patent_app_number] => 15/989920 [patent_app_country] => US [patent_app_date] => 2018-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5655 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15989920 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/989920
Methods and systems for parsing and executing instructions to retrieve data using autonomous memory May 24, 2018 Issued
Array ( [id] => 17269153 [patent_doc_number] => 11194578 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-07 [patent_title] => Fused overloaded register file read to enable 2-cycle move from condition register instruction in a microprocessor [patent_app_type] => utility [patent_app_number] => 15/987105 [patent_app_country] => US [patent_app_date] => 2018-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 8059 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15987105 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/987105
Fused overloaded register file read to enable 2-cycle move from condition register instruction in a microprocessor May 22, 2018 Issued
Array ( [id] => 13992103 [patent_doc_number] => 20190065209 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => BYTE AND NIBBLE SORT INSTRUCTIONS THAT PRODUCE SORTED DESTINATION REGISTER AND DESTINATION INDEX MAPPING [patent_app_type] => utility [patent_app_number] => 15/984739 [patent_app_country] => US [patent_app_date] => 2018-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12542 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15984739 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/984739
Byte and nibble sort instructions that produce sorted destination register and destination index mapping May 20, 2018 Issued
Array ( [id] => 14347625 [patent_doc_number] => 20190155785 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-23 [patent_title] => MULTI-CORE CONTROL SYSTEM [patent_app_type] => utility [patent_app_number] => 15/969964 [patent_app_country] => US [patent_app_date] => 2018-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8409 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15969964 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/969964
Multi-core control system that detects process dependencies and selectively reassigns processes May 2, 2018 Issued
Array ( [id] => 16355168 [patent_doc_number] => 10795678 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-06 [patent_title] => Matrix vector multiplier with a vector register file comprising a multi-port memory [patent_app_type] => utility [patent_app_number] => 15/959209 [patent_app_country] => US [patent_app_date] => 2018-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9484 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 304 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15959209 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/959209
Matrix vector multiplier with a vector register file comprising a multi-port memory Apr 20, 2018 Issued
Array ( [id] => 14175545 [patent_doc_number] => 10261787 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-16 [patent_title] => Multifunctional hexadecimal instruction form system and program product [patent_app_type] => utility [patent_app_number] => 15/957272 [patent_app_country] => US [patent_app_date] => 2018-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 5351 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15957272 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/957272
Multifunctional hexadecimal instruction form system and program product Apr 18, 2018 Issued
Array ( [id] => 16745088 [patent_doc_number] => 10970078 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-06 [patent_title] => Computation engine with upsize/interleave and downsize/deinterleave options [patent_app_type] => utility [patent_app_number] => 15/946719 [patent_app_country] => US [patent_app_date] => 2018-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7909 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15946719 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/946719
Computation engine with upsize/interleave and downsize/deinterleave options Apr 4, 2018 Issued
Array ( [id] => 15952731 [patent_doc_number] => 10664273 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-26 [patent_title] => Delayed prefetch manager to multicast an updated cache line to processor cores requesting the updated data [patent_app_type] => utility [patent_app_number] => 15/941958 [patent_app_country] => US [patent_app_date] => 2018-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 17102 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15941958 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/941958
Delayed prefetch manager to multicast an updated cache line to processor cores requesting the updated data Mar 29, 2018 Issued
Array ( [id] => 17824465 [patent_doc_number] => 11429413 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-30 [patent_title] => Method and apparatus to manage counter sets in a network interface controller [patent_app_type] => utility [patent_app_number] => 15/941483 [patent_app_country] => US [patent_app_date] => 2018-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7207 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15941483 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/941483
Method and apparatus to manage counter sets in a network interface controller Mar 29, 2018 Issued
Array ( [id] => 17786402 [patent_doc_number] => 11409525 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-09 [patent_title] => Apparatus and method for vector multiply and accumulate of packed words [patent_app_type] => utility [patent_app_number] => 15/879420 [patent_app_country] => US [patent_app_date] => 2018-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 14660 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15879420 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/879420
Apparatus and method for vector multiply and accumulate of packed words Jan 23, 2018 Issued
Array ( [id] => 14825195 [patent_doc_number] => 10409605 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-10 [patent_title] => System and method for using a branch mis-prediction buffer [patent_app_type] => utility [patent_app_number] => 15/877408 [patent_app_country] => US [patent_app_date] => 2018-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7740 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15877408 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/877408
System and method for using a branch mis-prediction buffer Jan 22, 2018 Issued
Array ( [id] => 13304333 [patent_doc_number] => 20180203703 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-19 [patent_title] => IMPLEMENTATION OF REGISTER RENAMING, CALL-RETURN PREDICTION AND PREFETCH [patent_app_type] => utility [patent_app_number] => 15/868497 [patent_app_country] => US [patent_app_date] => 2018-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7627 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15868497 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/868497
IMPLEMENTATION OF REGISTER RENAMING, CALL-RETURN PREDICTION AND PREFETCH Jan 10, 2018 Abandoned
Array ( [id] => 14061773 [patent_doc_number] => 10235179 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-19 [patent_title] => Data processor selecting a flag out of a plurality of flags generated by an instruction operating on multiple operand sizes in parallel [patent_app_type] => utility [patent_app_number] => 15/844212 [patent_app_country] => US [patent_app_date] => 2017-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 9444 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15844212 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/844212
Data processor selecting a flag out of a plurality of flags generated by an instruction operating on multiple operand sizes in parallel Dec 14, 2017 Issued
Array ( [id] => 14443533 [patent_doc_number] => 20190179640 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-13 [patent_title] => INSTRUCTION FUSION AFTER REGISTER RENAME [patent_app_type] => utility [patent_app_number] => 15/834413 [patent_app_country] => US [patent_app_date] => 2017-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6955 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15834413 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/834413
Instruction fusion after register rename Dec 6, 2017 Issued
Array ( [id] => 16683269 [patent_doc_number] => 10942747 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-09 [patent_title] => Head and tail pointer manipulation in a first-in-first-out issue queue [patent_app_type] => utility [patent_app_number] => 15/826738 [patent_app_country] => US [patent_app_date] => 2017-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7314 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15826738 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/826738
Head and tail pointer manipulation in a first-in-first-out issue queue Nov 29, 2017 Issued
Array ( [id] => 14379157 [patent_doc_number] => 20190163491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => COMPLETING COALESCED GLOBAL COMPLETION TABLE ENTRIES IN AN OUT-OF-ORDER PROCESSOR [patent_app_type] => utility [patent_app_number] => 15/826754 [patent_app_country] => US [patent_app_date] => 2017-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7825 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15826754 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/826754
Completing coalesced global completion table entries in an out-of-order processor Nov 29, 2017 Issued
Array ( [id] => 14161861 [patent_doc_number] => 20190108033 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-11 [patent_title] => LOAD-STORE UNIT WITH PARTITIONED REORDER QUEUES WITH SINGLE CAM PORT [patent_app_type] => utility [patent_app_number] => 15/825453 [patent_app_country] => US [patent_app_date] => 2017-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18425 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15825453 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/825453
Load-store unit with partitioned reorder queues with single cam port Nov 28, 2017 Issued
Array ( [id] => 16592479 [patent_doc_number] => 10901741 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-26 [patent_title] => Dynamic fusion of derived value creation and prediction of derived values in a subroutine branch sequence [patent_app_type] => utility [patent_app_number] => 15/819503 [patent_app_country] => US [patent_app_date] => 2017-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 34 [patent_no_of_words] => 19224 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15819503 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/819503
Dynamic fusion of derived value creation and prediction of derived values in a subroutine branch sequence Nov 20, 2017 Issued
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