Search

Jonathan Bradford

Examiner (ID: 11567, Phone: (571)270-5199 , Office: P/3744 )

Most Active Art Unit
3763
Art Unit(s)
3763, 4176, 3744
Total Applications
1374
Issued Applications
1024
Pending Applications
89
Abandoned Applications
296

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8691609 [patent_doc_number] => 08391140 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-05 [patent_title] => 'Deduplicated data processing rate control' [patent_app_type] => utility [patent_app_number] => 13/458772 [patent_app_country] => US [patent_app_date] => 2012-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6353 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13458772 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/458772
Deduplicated data processing rate control Apr 26, 2012 Issued
Array ( [id] => 9109876 [patent_doc_number] => 20130283008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-24 [patent_title] => '3-D STACKED MULTIPROCESSOR STRUCTURES AND METHODS FOR MULTIMODAL OPERATION OF SAME' [patent_app_type] => utility [patent_app_number] => 13/452078 [patent_app_country] => US [patent_app_date] => 2012-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12226 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13452078 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/452078
3-D stacked multiprocessor structure with vertically aligned identical layout operating processors in independent mode or in sharing mode running faster components Apr 19, 2012 Issued
Array ( [id] => 9592817 [patent_doc_number] => 08782381 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-15 [patent_title] => 'Dynamically rewriting branch instructions in response to cache line eviction' [patent_app_type] => utility [patent_app_number] => 13/444890 [patent_app_country] => US [patent_app_date] => 2012-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 16636 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13444890 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/444890
Dynamically rewriting branch instructions in response to cache line eviction Apr 11, 2012 Issued
Array ( [id] => 8325759 [patent_doc_number] => 20120198169 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-02 [patent_title] => 'Binary Rewriting in Software Instruction Cache' [patent_app_type] => utility [patent_app_number] => 13/442919 [patent_app_country] => US [patent_app_date] => 2012-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 16611 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13442919 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/442919
Dynamically rewriting branch instructions to directly target an instruction cache location Apr 9, 2012 Issued
Array ( [id] => 8315183 [patent_doc_number] => 20120192193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-26 [patent_title] => 'Executing An Application On A Parallel Computer' [patent_app_type] => utility [patent_app_number] => 13/440065 [patent_app_country] => US [patent_app_date] => 2012-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 12664 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13440065 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/440065
Parsing an application to find serial and parallel data segments to minimize mitigation overhead between serial and parallel compute nodes Apr 4, 2012 Issued
Array ( [id] => 8408062 [patent_doc_number] => 20120240130 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-20 [patent_title] => 'VIRTUAL WORLD SUBGROUP DETERMINATION AND SEGMENTATION FOR PERFORMANCE SCALABILITY' [patent_app_type] => utility [patent_app_number] => 13/431111 [patent_app_country] => US [patent_app_date] => 2012-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6742 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13431111 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/431111
Virtual world subgroup determination and segmentation for performance scalability Mar 26, 2012 Issued
Array ( [id] => 10543482 [patent_doc_number] => 09268614 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-23 [patent_title] => 'Configuring a parallel computer based on an interleave rate of an application containing serial and parallel segments' [patent_app_type] => utility [patent_app_number] => 13/426920 [patent_app_country] => US [patent_app_date] => 2012-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 13195 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13426920 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/426920
Configuring a parallel computer based on an interleave rate of an application containing serial and parallel segments Mar 21, 2012 Issued
Array ( [id] => 8291595 [patent_doc_number] => 20120179926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-12 [patent_title] => 'MEMORY CONTROL CIRCUIT AND INTEGRATED CIRCUIT INCLUDING BRANCH INSTRUCTION AND DETECTION AND OPERATION MODE CONTROL OF A MEMORY' [patent_app_type] => utility [patent_app_number] => 13/419318 [patent_app_country] => US [patent_app_date] => 2012-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8769 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13419318 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/419318
Memory control circuit and integrated circuit including branch instruction and detection and operation mode control of a memory Mar 12, 2012 Issued
Array ( [id] => 9781272 [patent_doc_number] => 08856493 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-07 [patent_title] => 'System of rotating data in a plurality of processing elements' [patent_app_type] => utility [patent_app_number] => 13/372683 [patent_app_country] => US [patent_app_date] => 2012-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 31 [patent_no_of_words] => 6349 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13372683 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/372683
System of rotating data in a plurality of processing elements Feb 13, 2012 Issued
Array ( [id] => 10536543 [patent_doc_number] => 09262173 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-16 [patent_title] => 'Critical section detection and prediction mechanism for hardware lock elision' [patent_app_type] => utility [patent_app_number] => 13/350572 [patent_app_country] => US [patent_app_date] => 2012-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9337 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13350572 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/350572
Critical section detection and prediction mechanism for hardware lock elision Jan 12, 2012 Issued
Array ( [id] => 8189186 [patent_doc_number] => 20120117353 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-10 [patent_title] => 'CLIENT PARTITION SCHEDULING AND PRIORITIZATION OF SERVICE PARTITION WORK' [patent_app_type] => utility [patent_app_number] => 13/349071 [patent_app_country] => US [patent_app_date] => 2012-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 10818 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20120117353.pdf [firstpage_image] =>[orig_patent_app_number] => 13349071 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/349071
Client partition scheduling and prioritization of service partition work Jan 11, 2012 Issued
Array ( [id] => 8201767 [patent_doc_number] => 20120124334 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-17 [patent_title] => 'SIMD PROCESSOR FOR PERFORMING DATA FILTERING AND/OR INTERPOLATION' [patent_app_type] => utility [patent_app_number] => 13/348358 [patent_app_country] => US [patent_app_date] => 2012-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6519 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20120124334.pdf [firstpage_image] =>[orig_patent_app_number] => 13348358 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/348358
SIMD processor for performing data filtering and/or interpolation Jan 10, 2012 Issued
Array ( [id] => 8279993 [patent_doc_number] => 20120173864 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-05 [patent_title] => 'FLEXIBLE MULTI-PROCESSING SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/342157 [patent_app_country] => US [patent_app_date] => 2012-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3138 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13342157 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/342157
FLEXIBLE MULTI-PROCESSING SYSTEM Jan 1, 2012 Abandoned
Array ( [id] => 12114344 [patent_doc_number] => 09870338 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-16 [patent_title] => 'Systems, apparatuses, and methods for performing vector packed compression and repeat' [patent_app_type] => utility [patent_app_number] => 13/992209 [patent_app_country] => US [patent_app_date] => 2011-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 25 [patent_no_of_words] => 16550 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13992209 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/992209
Systems, apparatuses, and methods for performing vector packed compression and repeat Dec 22, 2011 Issued
Array ( [id] => 9332540 [patent_doc_number] => 20140059322 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-27 [patent_title] => 'APPARATUS AND METHOD FOR BROADCASTING FROM A GENERAL PURPOSE REGISTER TO A VECTOR REGISTER' [patent_app_type] => utility [patent_app_number] => 13/996800 [patent_app_country] => US [patent_app_date] => 2011-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 15180 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13996800 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/996800
APPARATUS AND METHOD FOR BROADCASTING FROM A GENERAL PURPOSE REGISTER TO A VECTOR REGISTER Dec 22, 2011 Abandoned
Array ( [id] => 11179594 [patent_doc_number] => 09411586 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-09 [patent_title] => 'Apparatus and method for an instruction that determines whether a value is within a range' [patent_app_type] => utility [patent_app_number] => 13/996520 [patent_app_country] => US [patent_app_date] => 2011-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 27 [patent_no_of_words] => 15744 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13996520 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/996520
Apparatus and method for an instruction that determines whether a value is within a range Dec 22, 2011 Issued
Array ( [id] => 9193386 [patent_doc_number] => 20130332701 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-12 [patent_title] => 'APPARATUS AND METHOD FOR SELECTING ELEMENTS OF A VECTOR COMPUTATION' [patent_app_type] => utility [patent_app_number] => 13/996521 [patent_app_country] => US [patent_app_date] => 2011-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 14399 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13996521 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/996521
APPARATUS AND METHOD FOR SELECTING ELEMENTS OF A VECTOR COMPUTATION Dec 22, 2011 Abandoned
Array ( [id] => 8893698 [patent_doc_number] => 20130166882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-27 [patent_title] => 'METHODS AND APPARATUS FOR SCHEDULING INSTRUCTIONS WITHOUT INSTRUCTION DECODE' [patent_app_type] => utility [patent_app_number] => 13/335872 [patent_app_country] => US [patent_app_date] => 2011-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10005 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13335872 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/335872
METHODS AND APPARATUS FOR SCHEDULING INSTRUCTIONS WITHOUT INSTRUCTION DECODE Dec 21, 2011 Abandoned
Array ( [id] => 9372460 [patent_doc_number] => 20140082333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-20 [patent_title] => 'SYSTEMS, APPARATUSES, AND METHODS FOR PERFORMING AN ABSOLUTE DIFFERENCE CALCULATION BETWEEN CORRESPONDING PACKED DATA ELEMENTS OF TWO VECTOR REGISTERS' [patent_app_type] => utility [patent_app_number] => 13/996849 [patent_app_country] => US [patent_app_date] => 2011-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 15725 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13996849 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/996849
SYSTEMS, APPARATUSES, AND METHODS FOR PERFORMING AN ABSOLUTE DIFFERENCE CALCULATION BETWEEN CORRESPONDING PACKED DATA ELEMENTS OF TWO VECTOR REGISTERS Dec 21, 2011 Abandoned
Array ( [id] => 10637383 [patent_doc_number] => 09354886 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-31 [patent_title] => 'Maintaining the integrity of an execution return address stack' [patent_app_type] => utility [patent_app_number] => 13/304885 [patent_app_country] => US [patent_app_date] => 2011-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6276 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13304885 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/304885
Maintaining the integrity of an execution return address stack Nov 27, 2011 Issued
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