Search

Jonathan Cwern

Examiner (ID: 5747, Phone: (571)270-1560 , Office: P/3737 )

Most Active Art Unit
3737
Art Unit(s)
3797, 3737, 3793
Total Applications
910
Issued Applications
426
Pending Applications
90
Abandoned Applications
412

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17870448 [patent_doc_number] => 20220293185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => MEMORY CONTROL METHOD, MEMORY STORAGE DEVICE, AND MEMORY CONTROL CIRCUIT UNIT [patent_app_type] => utility [patent_app_number] => 17/214958 [patent_app_country] => US [patent_app_date] => 2021-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7895 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17214958 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/214958
Memory control method, memory storage device, and memory control circuit unit Mar 28, 2021 Issued
Array ( [id] => 16964739 [patent_doc_number] => 20210216238 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-15 [patent_title] => HIGH PERFORMANCE MEMORY MODULE WITH REDUCED LOADING [patent_app_type] => utility [patent_app_number] => 17/214770 [patent_app_country] => US [patent_app_date] => 2021-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3394 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17214770 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/214770
High performance memory module with reduced loading Mar 25, 2021 Issued
Array ( [id] => 17847726 [patent_doc_number] => 11437110 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-09-06 [patent_title] => Erase tail comparator scheme [patent_app_type] => utility [patent_app_number] => 17/212871 [patent_app_country] => US [patent_app_date] => 2021-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 25 [patent_no_of_words] => 15181 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17212871 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/212871
Erase tail comparator scheme Mar 24, 2021 Issued
Array ( [id] => 19765721 [patent_doc_number] => 12224019 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => Cache processes with adaptive dynamic start voltage calculation for memory devices [patent_app_type] => utility [patent_app_number] => 17/213150 [patent_app_country] => US [patent_app_date] => 2021-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 26744 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17213150 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/213150
Cache processes with adaptive dynamic start voltage calculation for memory devices Mar 24, 2021 Issued
Array ( [id] => 17085224 [patent_doc_number] => 20210280231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => MEMORY CELL IMPRINT AVOIDANCE [patent_app_type] => utility [patent_app_number] => 17/211246 [patent_app_country] => US [patent_app_date] => 2021-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18076 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17211246 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/211246
Memory cell imprint avoidance Mar 23, 2021 Issued
Array ( [id] => 18105295 [patent_doc_number] => 11545189 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-03 [patent_title] => Apparatuses and methods for different IO widths for stacked die [patent_app_type] => utility [patent_app_number] => 17/210922 [patent_app_country] => US [patent_app_date] => 2021-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6616 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17210922 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/210922
Apparatuses and methods for different IO widths for stacked die Mar 23, 2021 Issued
Array ( [id] => 18235765 [patent_doc_number] => 11600329 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-03-07 [patent_title] => Systems and methods for runtime analog sanitization of memory [patent_app_type] => utility [patent_app_number] => 17/207260 [patent_app_country] => US [patent_app_date] => 2021-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 7227 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17207260 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/207260
Systems and methods for runtime analog sanitization of memory Mar 18, 2021 Issued
Array ( [id] => 18119099 [patent_doc_number] => 11550492 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => Semiconductor memory device, controller, and memory system having semiconductor memory device and controller [patent_app_type] => utility [patent_app_number] => 17/204152 [patent_app_country] => US [patent_app_date] => 2021-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 26 [patent_no_of_words] => 11864 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17204152 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/204152
Semiconductor memory device, controller, and memory system having semiconductor memory device and controller Mar 16, 2021 Issued
Array ( [id] => 17870471 [patent_doc_number] => 20220293208 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => VOLTAGE CALIBRATION SCANS TO REDUCE MEMORY DEVICE OVERHEAD [patent_app_type] => utility [patent_app_number] => 17/198755 [patent_app_country] => US [patent_app_date] => 2021-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9357 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17198755 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/198755
Voltage calibration scans to reduce memory device overhead Mar 10, 2021 Issued
Array ( [id] => 17188533 [patent_doc_number] => 20210335418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/198375 [patent_app_country] => US [patent_app_date] => 2021-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 42795 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17198375 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/198375
Semiconductor memory device Mar 10, 2021 Issued
Array ( [id] => 17855308 [patent_doc_number] => 20220285351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => MULTIPLEXOR FOR A SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/190705 [patent_app_country] => US [patent_app_date] => 2021-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11288 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17190705 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/190705
Multiplexor for a semiconductor device Mar 2, 2021 Issued
Array ( [id] => 16904543 [patent_doc_number] => 20210183459 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => MEMORY DEVICE CAPABLE OF REDUCING PROGRAM DISTURBANCE AND ERASING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/187683 [patent_app_country] => US [patent_app_date] => 2021-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4138 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17187683 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/187683
Memory device capable of reducing program disturbance and erasing method thereof Feb 25, 2021 Issued
Array ( [id] => 17907197 [patent_doc_number] => 11461051 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-04 [patent_title] => Storage device and method of operating the same [patent_app_type] => utility [patent_app_number] => 17/183003 [patent_app_country] => US [patent_app_date] => 2021-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 15503 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17183003 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/183003
Storage device and method of operating the same Feb 22, 2021 Issued
Array ( [id] => 17833360 [patent_doc_number] => 20220270664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-25 [patent_title] => Selective Reference Voltage Calibration in Memory Subsystem [patent_app_type] => utility [patent_app_number] => 17/181979 [patent_app_country] => US [patent_app_date] => 2021-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11950 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17181979 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/181979
Selective reference voltage calibration in memory subsystem Feb 21, 2021 Issued
Array ( [id] => 16888649 [patent_doc_number] => 20210174846 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => SHIFT REGISTER, DRIVING METHOD THEREOF, GATE DRIVING CIRCUIT AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/179699 [patent_app_country] => US [patent_app_date] => 2021-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11329 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17179699 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/179699
Shift register, driving method thereof, gate driving circuit and display device Feb 18, 2021 Issued
Array ( [id] => 16872135 [patent_doc_number] => 20210165602 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-03 [patent_title] => WORD LINE CONTROL METHOD, WORD LINE CONTROL CIRCUIT DEVICE AND SEMICONDUCTOR MEMORY [patent_app_type] => utility [patent_app_number] => 17/171307 [patent_app_country] => US [patent_app_date] => 2021-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6037 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17171307 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/171307
Word line control method, word line control circuit device and semiconductor memory Feb 8, 2021 Issued
Array ( [id] => 17040405 [patent_doc_number] => 20210257041 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-19 [patent_title] => STORAGE DEVICE INCLUDING POWER SUPPLY CIRCUIT AND METHOD OF OPERATING STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 17/169643 [patent_app_country] => US [patent_app_date] => 2021-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10497 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17169643 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/169643
Storage device including power supply circuit and method of operating storage device Feb 7, 2021 Issued
Array ( [id] => 17395864 [patent_doc_number] => 11244888 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-08 [patent_title] => Memory core chip having TSVs [patent_app_type] => utility [patent_app_number] => 17/164454 [patent_app_country] => US [patent_app_date] => 2021-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 3960 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17164454 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/164454
Memory core chip having TSVs Jan 31, 2021 Issued
Array ( [id] => 18000724 [patent_doc_number] => 11501835 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-15 [patent_title] => Three-dimensional memory device and method of erasing thereof from a source side [patent_app_type] => utility [patent_app_number] => 17/158395 [patent_app_country] => US [patent_app_date] => 2021-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 35 [patent_no_of_words] => 16985 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17158395 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/158395
Three-dimensional memory device and method of erasing thereof from a source side Jan 25, 2021 Issued
Array ( [id] => 17698867 [patent_doc_number] => 11372591 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-28 [patent_title] => Memory apparatus, a semiconductor system including the same and an operating method thereof [patent_app_type] => utility [patent_app_number] => 17/157516 [patent_app_country] => US [patent_app_date] => 2021-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12076 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17157516 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/157516
Memory apparatus, a semiconductor system including the same and an operating method thereof Jan 24, 2021 Issued
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