Search

Jonathan Cwern

Examiner (ID: 5747, Phone: (571)270-1560 , Office: P/3737 )

Most Active Art Unit
3737
Art Unit(s)
3797, 3737, 3793
Total Applications
910
Issued Applications
426
Pending Applications
90
Abandoned Applications
412

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17977264 [patent_doc_number] => 11494123 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-08 [patent_title] => Memory system and control method thereof [patent_app_type] => utility [patent_app_number] => 17/150991 [patent_app_country] => US [patent_app_date] => 2021-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 24 [patent_no_of_words] => 8696 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17150991 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/150991
Memory system and control method thereof Jan 14, 2021 Issued
Array ( [id] => 17751383 [patent_doc_number] => 20220229588 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => NON-VOLATILE MEMORY WITH MEMORY ARRAY BETWEEN CIRCUITS [patent_app_type] => utility [patent_app_number] => 17/149867 [patent_app_country] => US [patent_app_date] => 2021-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21303 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17149867 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/149867
Non-volatile memory with memory array between circuits Jan 14, 2021 Issued
Array ( [id] => 17955050 [patent_doc_number] => 11481155 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-25 [patent_title] => Controller and operating method thereof [patent_app_type] => utility [patent_app_number] => 17/150641 [patent_app_country] => US [patent_app_date] => 2021-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 8954 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17150641 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/150641
Controller and operating method thereof Jan 14, 2021 Issued
Array ( [id] => 17708278 [patent_doc_number] => 20220208286 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => DYNAMIC DETECTION AND DYNAMIC ADJUSTMENT OF SUB-THRESHOLD SWING IN A MEMORY CELL SENSING CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/134010 [patent_app_country] => US [patent_app_date] => 2020-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15577 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17134010 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/134010
Dynamic detection and dynamic adjustment of sub-threshold swing in a memory cell sensing circuit Dec 23, 2020 Issued
Array ( [id] => 17690536 [patent_doc_number] => 20220197829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => HIGH CAPACITY HIDDEN MEMORY [patent_app_type] => utility [patent_app_number] => 17/128804 [patent_app_country] => US [patent_app_date] => 2020-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12495 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17128804 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/128804
HIGH CAPACITY HIDDEN MEMORY Dec 20, 2020 Abandoned
Array ( [id] => 16752281 [patent_doc_number] => 20210104293 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-08 [patent_title] => APPARATUSES AND METHODS FOR DIRECT ACCESS HYBRID TESTING [patent_app_type] => utility [patent_app_number] => 17/124169 [patent_app_country] => US [patent_app_date] => 2020-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9845 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17124169 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/124169
Apparatuses and methods for direct access hybrid testing Dec 15, 2020 Issued
Array ( [id] => 17977225 [patent_doc_number] => 11494084 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-08 [patent_title] => Managing dielectric stress of a memory device using controlled ramping slopes [patent_app_type] => utility [patent_app_number] => 17/119576 [patent_app_country] => US [patent_app_date] => 2020-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7678 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17119576 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/119576
Managing dielectric stress of a memory device using controlled ramping slopes Dec 10, 2020 Issued
Array ( [id] => 18645483 [patent_doc_number] => 11769561 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-26 [patent_title] => Non-volatile memory devices and systems with read-only memory features and methods for operating the same [patent_app_type] => utility [patent_app_number] => 17/119509 [patent_app_country] => US [patent_app_date] => 2020-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3105 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17119509 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/119509
Non-volatile memory devices and systems with read-only memory features and methods for operating the same Dec 10, 2020 Issued
Array ( [id] => 18408670 [patent_doc_number] => 20230170023 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-01 [patent_title] => METHOD FOR RESETTING AN ARRAY OF RESISTIVE MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 17/782446 [patent_app_country] => US [patent_app_date] => 2020-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3953 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17782446 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/782446
Method for resetting an array of resistive memory cells Dec 2, 2020 Issued
Array ( [id] => 18001133 [patent_doc_number] => 11502244 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-15 [patent_title] => Magnetic element [patent_app_type] => utility [patent_app_number] => 17/106905 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 9962 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17106905 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/106905
Magnetic element Nov 29, 2020 Issued
Array ( [id] => 17645053 [patent_doc_number] => 20220172792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-02 [patent_title] => METHOD AND SYSTEM FOR VALIDATING ERASURE STATUS OF DATA BLOCKS [patent_app_type] => utility [patent_app_number] => 17/106320 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4453 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17106320 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/106320
Method and system for validating erasure status of data blocks Nov 29, 2020 Issued
Array ( [id] => 16715372 [patent_doc_number] => 20210082519 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/103504 [patent_app_country] => US [patent_app_date] => 2020-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14225 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 304 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17103504 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/103504
Semiconductor memory device Nov 23, 2020 Issued
Array ( [id] => 16850347 [patent_doc_number] => 20210151092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-20 [patent_title] => SUB-WORD LINE DRIVER WITH SOFT-LANDING [patent_app_type] => utility [patent_app_number] => 16/953015 [patent_app_country] => US [patent_app_date] => 2020-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15394 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16953015 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/953015
Sub-word line driver with soft-landing Nov 18, 2020 Issued
Array ( [id] => 18578690 [patent_doc_number] => 11735229 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-22 [patent_title] => Multi-die stacked package memory and output synchronization method thereof [patent_app_type] => utility [patent_app_number] => 17/296974 [patent_app_country] => US [patent_app_date] => 2020-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2709 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 300 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17296974 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/296974
Multi-die stacked package memory and output synchronization method thereof Nov 10, 2020 Issued
Array ( [id] => 17757252 [patent_doc_number] => 11397544 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-26 [patent_title] => Multi-terminal neuromorphic device [patent_app_type] => utility [patent_app_number] => 17/094708 [patent_app_country] => US [patent_app_date] => 2020-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 6872 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17094708 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/094708
Multi-terminal neuromorphic device Nov 9, 2020 Issued
Array ( [id] => 17599071 [patent_doc_number] => 20220148645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-12 [patent_title] => APPARATUS WITH REFRESH MANAGEMENT MECHANISM [patent_app_type] => utility [patent_app_number] => 17/091969 [patent_app_country] => US [patent_app_date] => 2020-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9554 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17091969 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/091969
Apparatus with refresh management mechanism Nov 5, 2020 Issued
Array ( [id] => 17493541 [patent_doc_number] => 11282858 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-22 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 17/087724 [patent_app_country] => US [patent_app_date] => 2020-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 8892 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17087724 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/087724
Semiconductor memory device Nov 2, 2020 Issued
Array ( [id] => 17861499 [patent_doc_number] => 11442655 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-13 [patent_title] => Semiconductor device and method of operating the same [patent_app_type] => utility [patent_app_number] => 17/083500 [patent_app_country] => US [patent_app_date] => 2020-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9663 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17083500 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/083500
Semiconductor device and method of operating the same Oct 28, 2020 Issued
Array ( [id] => 16615901 [patent_doc_number] => 20210034554 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-04 [patent_title] => METHODS FOR PERFORMING MULTIPLE MEMORY OPERATIONS IN RESPONSE TO A SINGLE COMMAND AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME [patent_app_type] => utility [patent_app_number] => 17/074281 [patent_app_country] => US [patent_app_date] => 2020-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5097 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17074281 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/074281
Methods for performing multiple memory operations in response to a single command and memory devices and systems employing the same Oct 18, 2020 Issued
Array ( [id] => 17542646 [patent_doc_number] => 11307767 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-04-19 [patent_title] => System for controlling memory operations in system-on-chips [patent_app_type] => utility [patent_app_number] => 17/071892 [patent_app_country] => US [patent_app_date] => 2020-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 13580 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17071892 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/071892
System for controlling memory operations in system-on-chips Oct 14, 2020 Issued
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