
Jonathan Cwern
Examiner (ID: 5747, Phone: (571)270-1560 , Office: P/3737 )
| Most Active Art Unit | 3737 |
| Art Unit(s) | 3797, 3737, 3793 |
| Total Applications | 910 |
| Issued Applications | 426 |
| Pending Applications | 90 |
| Abandoned Applications | 412 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19347883
[patent_doc_number] => 20240256847
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-01
[patent_title] => ANALOG NEUROMORPHIC CIRCUITS FOR DOT-PRODUCT OPERATION IMPLEMENTING RESISTIVE MEMORIES
[patent_app_type] => utility
[patent_app_number] => 18/631003
[patent_app_country] => US
[patent_app_date] => 2024-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 22066
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18631003
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/631003 | Analog neuromorphic circuits for dot-product operation implementing resistive memories | Apr 8, 2024 | Issued |
Array
(
[id] => 20026926
[patent_doc_number] => 20250165148
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-05-22
[patent_title] => PREDICTION OF DATA RETENTION DEGRADATION OF A NON-VOLATILE MEMORY DEVICE BASED ON A MACHINE LEARNING ALGORITHM
[patent_app_type] => utility
[patent_app_number] => 18/622866
[patent_app_country] => US
[patent_app_date] => 2024-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5440
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 180
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18622866
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/622866 | PREDICTION OF DATA RETENTION DEGRADATION OF A NON-VOLATILE MEMORY DEVICE BASED ON A MACHINE LEARNING ALGORITHM | Mar 28, 2024 | Pending |
Array
(
[id] => 20249646
[patent_doc_number] => 20250298515
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-09-25
[patent_title] => LOW-OVERHEAD PERIODIC ADJUSTMENT FOR MEMORY TIMING
[patent_app_type] => utility
[patent_app_number] => 18/614187
[patent_app_country] => US
[patent_app_date] => 2024-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8510
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18614187
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/614187 | LOW-OVERHEAD PERIODIC ADJUSTMENT FOR MEMORY TIMING | Mar 21, 2024 | Pending |
Array
(
[id] => 19285363
[patent_doc_number] => 20240221840
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-04
[patent_title] => MULTI-PROGRAM OF MEMORY CELLS WITHOUT INTERVENING ERASE OPERATIONS
[patent_app_type] => utility
[patent_app_number] => 18/604858
[patent_app_country] => US
[patent_app_date] => 2024-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11967
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18604858
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/604858 | Multi-program of memory cells without intervening erase operations | Mar 13, 2024 | Issued |
Array
(
[id] => 20317956
[patent_doc_number] => 12456511
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-10-28
[patent_title] => Memory circuit and method of operating same
[patent_app_type] => utility
[patent_app_number] => 18/601367
[patent_app_country] => US
[patent_app_date] => 2024-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 22775
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 197
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18601367
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/601367 | Memory circuit and method of operating same | Mar 10, 2024 | Issued |
Array
(
[id] => 20222738
[patent_doc_number] => 20250285669
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-09-11
[patent_title] => MAGNETIC TUNNEL JUNCTION WITH DUAL REFERENCE LAYERS HAVING PARALLEL MAGNETIZATION DIRECTIONS AND METHODS FOR OPERATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/600384
[patent_app_country] => US
[patent_app_date] => 2024-03-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1113
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18600384
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/600384 | MAGNETIC TUNNEL JUNCTION WITH DUAL REFERENCE LAYERS HAVING PARALLEL MAGNETIZATION DIRECTIONS AND METHODS FOR OPERATING THE SAME | Mar 7, 2024 | Pending |
Array
(
[id] => 19252492
[patent_doc_number] => 20240203489
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-20
[patent_title] => INTEGRATED CIRCUIT DEVICE INCLUDING AN SRAM PORTION HAVING END POWER SELECT CIRCUITS
[patent_app_type] => utility
[patent_app_number] => 18/592833
[patent_app_country] => US
[patent_app_date] => 2024-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9162
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 185
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18592833
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/592833 | Integrated circuit device including an SRAM portion having end power select circuits | Feb 29, 2024 | Issued |
Array
(
[id] => 19252471
[patent_doc_number] => 20240203468
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-20
[patent_title] => ADAPTIVE WRITE OPERATIONS FOR A MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/593635
[patent_app_country] => US
[patent_app_date] => 2024-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 18702
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18593635
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/593635 | Adaptive write operations for a memory device | Feb 29, 2024 | Issued |
Array
(
[id] => 20043033
[patent_doc_number] => 20250181255
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-06-05
[patent_title] => PROGRAM SPEED COMPENSATION FOR NON-VOLATILE MEMORY CELLS
[patent_app_type] => utility
[patent_app_number] => 18/586350
[patent_app_country] => US
[patent_app_date] => 2024-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2601
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18586350
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/586350 | Program speed compensation for non-volatile memory cells | Feb 22, 2024 | Issued |
Array
(
[id] => 20345804
[patent_doc_number] => 12469539
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-11-11
[patent_title] => Apparatus with refresh management mechanism
[patent_app_type] => utility
[patent_app_number] => 18/583527
[patent_app_country] => US
[patent_app_date] => 2024-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4427
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18583527
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/583527 | Apparatus with refresh management mechanism | Feb 20, 2024 | Issued |
Array
(
[id] => 19696100
[patent_doc_number] => 20250014645
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-09
[patent_title] => NONVOLATILE MEMORY DEVICES AND MEMORY PACKAGES INCLUDING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/443463
[patent_app_country] => US
[patent_app_date] => 2024-02-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 22570
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18443463
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/443463 | NONVOLATILE MEMORY DEVICES AND MEMORY PACKAGES INCLUDING THE SAME | Feb 15, 2024 | Pending |
Array
(
[id] => 20373992
[patent_doc_number] => 12481425
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-11-25
[patent_title] => Determining reference voltage offsets for read operations in a memory system
[patent_app_type] => utility
[patent_app_number] => 18/429139
[patent_app_country] => US
[patent_app_date] => 2024-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 10870
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 151
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18429139
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/429139 | Determining reference voltage offsets for read operations in a memory system | Jan 30, 2024 | Issued |
Array
(
[id] => 20139168
[patent_doc_number] => 20250246212
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-07-31
[patent_title] => MAGNETIC DOMAIN WALL MOTION ELEMENT AND MAGNETIC ARRAY
[patent_app_type] => utility
[patent_app_number] => 18/426708
[patent_app_country] => US
[patent_app_date] => 2024-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5882
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 195
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18426708
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/426708 | Magnetic domain wall motion element and magnetic array | Jan 29, 2024 | Issued |
Array
(
[id] => 19500127
[patent_doc_number] => 20240339145
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-10
[patent_title] => MEMORY DEVICE AND OPERATION METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/422770
[patent_app_country] => US
[patent_app_date] => 2024-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14112
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18422770
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/422770 | Memory device and operation method thereof | Jan 24, 2024 | Issued |
Array
(
[id] => 19160853
[patent_doc_number] => 20240153560
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-09
[patent_title] => NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/414524
[patent_app_country] => US
[patent_app_date] => 2024-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15444
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => 0
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18414524
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/414524 | Nonvolatile semiconductor memory device | Jan 16, 2024 | Issued |
Array
(
[id] => 20217624
[patent_doc_number] => 12414293
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-09-09
[patent_title] => Antifuse-type one time programming memory with forksheet transistors
[patent_app_type] => utility
[patent_app_number] => 18/413085
[patent_app_country] => US
[patent_app_date] => 2024-01-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 25
[patent_no_of_words] => 13230
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 319
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18413085
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/413085 | Antifuse-type one time programming memory with forksheet transistors | Jan 15, 2024 | Issued |
Array
(
[id] => 20553246
[patent_doc_number] => 12564061
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-02-24
[patent_title] => Generation of physically unclonable function using one-time-programmable memory devices with back-end-of-line transistors
[patent_app_type] => utility
[patent_app_number] => 18/412505
[patent_app_country] => US
[patent_app_date] => 2024-01-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 7772
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18412505
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/412505 | Generation of physically unclonable function using one-time-programmable memory devices with back-end-of-line transistors | Jan 12, 2024 | Issued |
Array
(
[id] => 20552915
[patent_doc_number] => 12563723
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-02-24
[patent_title] => Efuse cells with backside power rails
[patent_app_type] => utility
[patent_app_number] => 18/410190
[patent_app_country] => US
[patent_app_date] => 2024-01-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 28
[patent_no_of_words] => 8901
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18410190
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/410190 | Efuse cells with backside power rails | Jan 10, 2024 | Issued |
Array
(
[id] => 19145989
[patent_doc_number] => 20240145004
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-02
[patent_title] => THREE-DIMENSIONAL FLASH MEMORY AND OPERATION METHOD THEREFOR
[patent_app_type] => utility
[patent_app_number] => 18/407533
[patent_app_country] => US
[patent_app_date] => 2024-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17232
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18407533
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/407533 | Three-dimensional flash memory and operation method therefor | Jan 8, 2024 | Issued |
Array
(
[id] => 19160846
[patent_doc_number] => 20240153553
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-09
[patent_title] => NON-VOLATILE PHASE-CHANGE MEMORY DEVICE INCLUDING A DISTRIBUTED ROW DECODER WITH N-CHANNEL MOSFET TRANSISTORS AND RELATED ROW DECODING METHOD
[patent_app_type] => utility
[patent_app_number] => 18/406097
[patent_app_country] => US
[patent_app_date] => 2024-01-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5863
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18406097
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/406097 | Non-volatile phase-change memory device including a distributed row decoder with n-channel MOSFET transistors and related row decoding method | Jan 5, 2024 | Issued |