Search

Jonathan G. Jelsma

Examiner (ID: 15225)

Most Active Art Unit
1722
Art Unit(s)
1722, 1795, 1721
Total Applications
1007
Issued Applications
655
Pending Applications
83
Abandoned Applications
290

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20509264 [patent_doc_number] => 12543557 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-03 [patent_title] => System and method to reduce layout dimensions using non-perpendicular process scheme [patent_app_type] => utility [patent_app_number] => 17/566564 [patent_app_country] => US [patent_app_date] => 2021-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 25 [patent_no_of_words] => 5511 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17566564 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/566564
System and method to reduce layout dimensions using non-perpendicular process scheme Dec 29, 2021 Issued
Array ( [id] => 18548223 [patent_doc_number] => 11721582 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Method of making 3D circuits with integrated stacked 3D metal lines for high density circuits [patent_app_type] => utility [patent_app_number] => 17/557561 [patent_app_country] => US [patent_app_date] => 2021-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 5850 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17557561 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/557561
Method of making 3D circuits with integrated stacked 3D metal lines for high density circuits Dec 20, 2021 Issued
Array ( [id] => 18456325 [patent_doc_number] => 20230197607 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => LINE FORMATION WITH SMALL TIP SPACING [patent_app_type] => utility [patent_app_number] => 17/554799 [patent_app_country] => US [patent_app_date] => 2021-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5769 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17554799 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/554799
LINE FORMATION WITH SMALL TIP SPACING Dec 16, 2021 Abandoned
Array ( [id] => 17660934 [patent_doc_number] => 20220181399 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => Electroluminescence Display Apparatus [patent_app_type] => utility [patent_app_number] => 17/543522 [patent_app_country] => US [patent_app_date] => 2021-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10849 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17543522 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/543522
Electroluminescence display apparatus Dec 5, 2021 Issued
Array ( [id] => 17949341 [patent_doc_number] => 20220336360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => DIAGONAL VIAS IN SEMICONDUCTOR STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/543518 [patent_app_country] => US [patent_app_date] => 2021-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12081 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17543518 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/543518
Diagonal vias in semiconductor structures Dec 5, 2021 Issued
Array ( [id] => 17709190 [patent_doc_number] => 20220209198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => LIGHT EMITTING DISPLAY APPARATUS [patent_app_type] => utility [patent_app_number] => 17/532680 [patent_app_country] => US [patent_app_date] => 2021-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12803 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17532680 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/532680
Light emitting display apparatus Nov 21, 2021 Issued
Array ( [id] => 17463683 [patent_doc_number] => 20220076989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-10 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME [patent_app_type] => utility [patent_app_number] => 17/530561 [patent_app_country] => US [patent_app_date] => 2021-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5784 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17530561 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/530561
Semiconductor structure and method for forming same Nov 18, 2021 Issued
Array ( [id] => 18563024 [patent_doc_number] => 11728277 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-15 [patent_title] => Method for manufacturing semiconductor structure having via through bonded wafers [patent_app_type] => utility [patent_app_number] => 17/529507 [patent_app_country] => US [patent_app_date] => 2021-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 21 [patent_no_of_words] => 6969 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 383 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17529507 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/529507
Method for manufacturing semiconductor structure having via through bonded wafers Nov 17, 2021 Issued
Array ( [id] => 19796244 [patent_doc_number] => 12237213 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-25 [patent_title] => Method for manufacturing semiconductor device [patent_app_type] => utility [patent_app_number] => 17/631932 [patent_app_country] => US [patent_app_date] => 2021-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 4983 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17631932 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/631932
Method for manufacturing semiconductor device Nov 11, 2021 Issued
Array ( [id] => 17448421 [patent_doc_number] => 20220068926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/454249 [patent_app_country] => US [patent_app_date] => 2021-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5074 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17454249 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/454249
Method of manufacturing semiconductor device Nov 9, 2021 Issued
Array ( [id] => 18562464 [patent_doc_number] => 11727714 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-15 [patent_title] => Fingerprint sensor device and method [patent_app_type] => utility [patent_app_number] => 17/522610 [patent_app_country] => US [patent_app_date] => 2021-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 12586 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17522610 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/522610
Fingerprint sensor device and method Nov 8, 2021 Issued
Array ( [id] => 17448013 [patent_doc_number] => 20220068518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => METHOD OF MANUFACTURING AN ELECTRONIC DEVICE AND CONDUCTIVE PASTE FOR THE SAME [patent_app_type] => utility [patent_app_number] => 17/454098 [patent_app_country] => US [patent_app_date] => 2021-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6060 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17454098 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/454098
METHOD OF MANUFACTURING AN ELECTRONIC DEVICE AND CONDUCTIVE PASTE FOR THE SAME Nov 8, 2021 Abandoned
Array ( [id] => 19108626 [patent_doc_number] => 11961740 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-16 [patent_title] => Manufacturing method for integrating gate dielectric layers of different thicknesses [patent_app_type] => utility [patent_app_number] => 17/516589 [patent_app_country] => US [patent_app_date] => 2021-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 3691 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17516589 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/516589
Manufacturing method for integrating gate dielectric layers of different thicknesses Oct 31, 2021 Issued
Array ( [id] => 17870729 [patent_doc_number] => 20220293466 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => Method for Forming Semiconductor Structure and Semiconductor Structure [patent_app_type] => utility [patent_app_number] => 17/452460 [patent_app_country] => US [patent_app_date] => 2021-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3853 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17452460 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/452460
Method for Forming Semiconductor Structure and Semiconductor Structure Oct 26, 2021 Abandoned
Array ( [id] => 20496626 [patent_doc_number] => 12538516 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-27 [patent_title] => Forksheet transistor with asymmetric dielectric spine [patent_app_type] => utility [patent_app_number] => 17/509223 [patent_app_country] => US [patent_app_date] => 2021-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 5781 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17509223 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/509223
Forksheet transistor with asymmetric dielectric spine Oct 24, 2021 Issued
Array ( [id] => 17900729 [patent_doc_number] => 20220310391 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => METHOD FOR MANUFACTURING MASK STRUCTURE, SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/451967 [patent_app_country] => US [patent_app_date] => 2021-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5980 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17451967 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/451967
Method for manufacturing mask structure, semiconductor structure and manufacturing method thereof Oct 21, 2021 Issued
Array ( [id] => 17389516 [patent_doc_number] => 20220037368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-03 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/501084 [patent_app_country] => US [patent_app_date] => 2021-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22204 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17501084 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/501084
Semiconductor device and manufacturing method thereof Oct 13, 2021 Issued
Array ( [id] => 17389495 [patent_doc_number] => 20220037347 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-03 [patent_title] => SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 17/501149 [patent_app_country] => US [patent_app_date] => 2021-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7391 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17501149 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/501149
Semiconductor devices Oct 13, 2021 Issued
Array ( [id] => 18317533 [patent_doc_number] => 11631617 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-18 [patent_title] => Scalable device for FINFET technology [patent_app_type] => utility [patent_app_number] => 17/501924 [patent_app_country] => US [patent_app_date] => 2021-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 35 [patent_no_of_words] => 8731 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17501924 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/501924
Scalable device for FINFET technology Oct 13, 2021 Issued
Array ( [id] => 18263104 [patent_doc_number] => 11610813 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-21 [patent_title] => Interconnection element and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/488714 [patent_app_country] => US [patent_app_date] => 2021-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 6074 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17488714 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/488714
Interconnection element and method of manufacturing the same Sep 28, 2021 Issued
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