Search

Jonathan G. Jelsma

Examiner (ID: 15225)

Most Active Art Unit
1722
Art Unit(s)
1722, 1795, 1721
Total Applications
1007
Issued Applications
655
Pending Applications
83
Abandoned Applications
290

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17978601 [patent_doc_number] => 11495473 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-08 [patent_title] => Semiconductor device and manufacturing method of semiconductor device [patent_app_type] => utility [patent_app_number] => 17/161168 [patent_app_country] => US [patent_app_date] => 2021-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 35 [patent_no_of_words] => 6973 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17161168 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/161168
Semiconductor device and manufacturing method of semiconductor device Jan 27, 2021 Issued
Array ( [id] => 17347207 [patent_doc_number] => 20220013538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-13 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/158494 [patent_app_country] => US [patent_app_date] => 2021-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10472 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17158494 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/158494
Semiconductor memory device Jan 25, 2021 Issued
Array ( [id] => 19139438 [patent_doc_number] => 11974430 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-30 [patent_title] => Microelectronic devices with dopant extensions near a GIDL region below a tier stack, and related methods and systems [patent_app_type] => utility [patent_app_number] => 17/158859 [patent_app_country] => US [patent_app_date] => 2021-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 31 [patent_no_of_words] => 19683 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17158859 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/158859
Microelectronic devices with dopant extensions near a GIDL region below a tier stack, and related methods and systems Jan 25, 2021 Issued
Array ( [id] => 19294555 [patent_doc_number] => 12033919 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-09 [patent_title] => Backside or frontside through substrate via (TSV) landing on metal [patent_app_type] => utility [patent_app_number] => 17/144717 [patent_app_country] => US [patent_app_date] => 2021-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 25 [patent_no_of_words] => 7590 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17144717 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/144717
Backside or frontside through substrate via (TSV) landing on metal Jan 7, 2021 Issued
Array ( [id] => 18343452 [patent_doc_number] => 11640936 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-02 [patent_title] => Interconnect structures and methods of fabrication thereof [patent_app_type] => utility [patent_app_number] => 17/144724 [patent_app_country] => US [patent_app_date] => 2021-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 8111 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17144724 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/144724
Interconnect structures and methods of fabrication thereof Jan 7, 2021 Issued
Array ( [id] => 17599335 [patent_doc_number] => 20220148909 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-12 [patent_title] => Method for Improving HDP Filling Defects through STI Etching Process [patent_app_type] => utility [patent_app_number] => 17/142623 [patent_app_country] => US [patent_app_date] => 2021-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4027 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 300 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17142623 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/142623
Method for improving HDP filling defects through STI etching process Jan 5, 2021 Issued
Array ( [id] => 18950961 [patent_doc_number] => 11894267 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-06 [patent_title] => Method for fabricating integrated circuit device [patent_app_type] => utility [patent_app_number] => 17/141852 [patent_app_country] => US [patent_app_date] => 2021-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 28 [patent_no_of_words] => 12079 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17141852 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/141852
Method for fabricating integrated circuit device Jan 4, 2021 Issued
Array ( [id] => 17978618 [patent_doc_number] => 11495490 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-08 [patent_title] => Semiconductor device manufacturing method [patent_app_type] => utility [patent_app_number] => 17/137945 [patent_app_country] => US [patent_app_date] => 2020-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 74 [patent_no_of_words] => 8563 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17137945 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/137945
Semiconductor device manufacturing method Dec 29, 2020 Issued
Array ( [id] => 18156391 [patent_doc_number] => 11569386 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-31 [patent_title] => Method for forming semiconductor device structure with cap layer [patent_app_type] => utility [patent_app_number] => 17/135316 [patent_app_country] => US [patent_app_date] => 2020-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 5766 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17135316 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/135316
Method for forming semiconductor device structure with cap layer Dec 27, 2020 Issued
Array ( [id] => 17692466 [patent_doc_number] => 20220199759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => DEEP TRENCH CAPACITOR INCLUDING SELF-ALIGNED PLATE CONTACT VIA STRUCTURES AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/126294 [patent_app_country] => US [patent_app_date] => 2020-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12854 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17126294 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/126294
Deep trench capacitor including self-aligned plate contact via structures and methods of forming the same Dec 17, 2020 Issued
Array ( [id] => 17758249 [patent_doc_number] => 11398548 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-26 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/124124 [patent_app_country] => US [patent_app_date] => 2020-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 6095 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17124124 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/124124
Semiconductor device Dec 15, 2020 Issued
Array ( [id] => 18236009 [patent_doc_number] => 11600574 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-07 [patent_title] => Method of forming RDLS and structure formed thereof [patent_app_type] => utility [patent_app_number] => 17/121020 [patent_app_country] => US [patent_app_date] => 2020-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 35 [patent_no_of_words] => 9076 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17121020 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/121020
Method of forming RDLS and structure formed thereof Dec 13, 2020 Issued
Array ( [id] => 16731214 [patent_doc_number] => 20210098362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => Method and Apparatus for Forming Self-Aligned Via with Selectively Deposited Etching Stop Layer [patent_app_type] => utility [patent_app_number] => 17/120601 [patent_app_country] => US [patent_app_date] => 2020-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5917 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17120601 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/120601
Method and apparatus for forming self-aligned via with selectively deposited etching stop layer Dec 13, 2020 Issued
Array ( [id] => 17758131 [patent_doc_number] => 11398430 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-26 [patent_title] => Package device and a manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/114507 [patent_app_country] => US [patent_app_date] => 2020-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6840 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17114507 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/114507
Package device and a manufacturing method thereof Dec 7, 2020 Issued
Array ( [id] => 17787722 [patent_doc_number] => 11410856 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-09 [patent_title] => Chip packaging method [patent_app_type] => utility [patent_app_number] => 17/109540 [patent_app_country] => US [patent_app_date] => 2020-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2450 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17109540 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/109540
Chip packaging method Dec 1, 2020 Issued
Array ( [id] => 16715772 [patent_doc_number] => 20210082919 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => Replacement Gate Process for FinFET [patent_app_type] => utility [patent_app_number] => 17/106880 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6021 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17106880 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/106880
Replacement gate process for FinFET Nov 29, 2020 Issued
Array ( [id] => 20347684 [patent_doc_number] => 12471422 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Optoelectronic device and method for producing an optoelectronic device [patent_app_type] => utility [patent_app_number] => 17/782545 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 0 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17782545 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/782545
Optoelectronic device and method for producing an optoelectronic device Nov 29, 2020 Issued
Array ( [id] => 16692100 [patent_doc_number] => 20210074579 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-11 [patent_title] => Semiconductor Device and Method [patent_app_type] => utility [patent_app_number] => 17/101131 [patent_app_country] => US [patent_app_date] => 2020-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9883 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17101131 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/101131
Semiconductor device and method Nov 22, 2020 Issued
Array ( [id] => 16692213 [patent_doc_number] => 20210074692 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-11 [patent_title] => INTERPOSER FRAME AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 16/953871 [patent_app_country] => US [patent_app_date] => 2020-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4151 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16953871 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/953871
Interposer frame and method of manufacturing the same Nov 19, 2020 Issued
Array ( [id] => 17878710 [patent_doc_number] => 11450735 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-20 [patent_title] => Method of forming guard ring and circuit device [patent_app_type] => utility [patent_app_number] => 16/952305 [patent_app_country] => US [patent_app_date] => 2020-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 6315 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16952305 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/952305
Method of forming guard ring and circuit device Nov 18, 2020 Issued
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