Search

Jonathan G. Jelsma

Examiner (ID: 15225)

Most Active Art Unit
1722
Art Unit(s)
1722, 1795, 1721
Total Applications
1007
Issued Applications
655
Pending Applications
83
Abandoned Applications
290

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14558569 [patent_doc_number] => 10347757 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-09 [patent_title] => Lateral MOSFET [patent_app_type] => utility [patent_app_number] => 16/177808 [patent_app_country] => US [patent_app_date] => 2018-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 4799 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16177808 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/177808
Lateral MOSFET Oct 31, 2018 Issued
Array ( [id] => 14676787 [patent_doc_number] => 20190237508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/169483 [patent_app_country] => US [patent_app_date] => 2018-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7562 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16169483 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/169483
Display device Oct 23, 2018 Issued
Array ( [id] => 16495781 [patent_doc_number] => 10861833 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-08 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 16/160692 [patent_app_country] => US [patent_app_date] => 2018-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4655 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16160692 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/160692
Semiconductor device Oct 14, 2018 Issued
Array ( [id] => 15775695 [patent_doc_number] => 20200118865 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => CONTROLLING PERFORMANCE AND RELIABILITY OF CONDUCTIVE REGIONS IN A METALLIZATION NETWORK [patent_app_type] => utility [patent_app_number] => 16/157286 [patent_app_country] => US [patent_app_date] => 2018-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4950 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16157286 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/157286
Controlling performance and reliability of conductive regions in a metallization network Oct 10, 2018 Issued
Array ( [id] => 15331821 [patent_doc_number] => 20200006240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => Method of Forming RDLS and Structure Formed Thereof [patent_app_type] => utility [patent_app_number] => 16/157391 [patent_app_country] => US [patent_app_date] => 2018-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9056 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16157391 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/157391
Method of forming RDLS and structure formed thereof Oct 10, 2018 Issued
Array ( [id] => 15775745 [patent_doc_number] => 20200118890 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => SELF-ALIGNED TOP SPACERS FOR VERTICAL FETS WITH IN SITU SOLID STATE DOPING [patent_app_type] => utility [patent_app_number] => 16/157786 [patent_app_country] => US [patent_app_date] => 2018-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5719 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16157786 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/157786
Self-aligned top spacers for vertical FETs with in situ solid state doping Oct 10, 2018 Issued
Array ( [id] => 15775741 [patent_doc_number] => 20200118888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => GATE FORMATION SCHEME FOR N-TYPE AND P-TYPE TRANSISTORS HAVING SEPARATELY TUNED THRESHOLD VOLTAGES [patent_app_type] => utility [patent_app_number] => 16/157325 [patent_app_country] => US [patent_app_date] => 2018-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7514 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16157325 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/157325
Gate formation scheme for n-type and p-type transistors having separately tuned threshold voltages Oct 10, 2018 Issued
Array ( [id] => 13909389 [patent_doc_number] => 20190043899 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-07 [patent_title] => METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/157158 [patent_app_country] => US [patent_app_date] => 2018-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16959 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16157158 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/157158
Method for manufacturing semiconductor device Oct 10, 2018 Issued
Array ( [id] => 15169965 [patent_doc_number] => 10490486 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-26 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 16/140791 [patent_app_country] => US [patent_app_date] => 2018-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 27 [patent_no_of_words] => 11735 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 382 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16140791 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/140791
Semiconductor device Sep 24, 2018 Issued
Array ( [id] => 15462741 [patent_doc_number] => 20200044195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-06 [patent_title] => METHOD OF MANUFACTURING A THIN FILM ENCAPSULATION LAYER AND ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/307859 [patent_app_country] => US [patent_app_date] => 2018-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3606 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16307859 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/307859
Method of manufacturing a thin film encapsulation layer and organic light emitting diode display device Sep 6, 2018 Issued
Array ( [id] => 13786087 [patent_doc_number] => 20190006582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-03 [patent_title] => Memory Cell Having Magnetic Tunnel Junction and Thermal Stability Enhancement Layer [patent_app_type] => utility [patent_app_number] => 16/123663 [patent_app_country] => US [patent_app_date] => 2018-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6972 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -32 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16123663 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/123663
Memory cell having magnetic tunnel junction and thermal stability enhancement layer Sep 5, 2018 Issued
Array ( [id] => 14137857 [patent_doc_number] => 20190103318 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-04 [patent_title] => SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/117634 [patent_app_country] => US [patent_app_date] => 2018-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9880 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16117634 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/117634
Semiconductor structure and fabrication method thereof Aug 29, 2018 Issued
Array ( [id] => 14317063 [patent_doc_number] => 20190148235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-16 [patent_title] => SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/117804 [patent_app_country] => US [patent_app_date] => 2018-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7546 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16117804 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/117804
Semiconductor device and fabrication method thereof Aug 29, 2018 Issued
Array ( [id] => 17652646 [patent_doc_number] => 11355386 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-07 [patent_title] => Method for manufacturing a semiconductor device and semiconductor device [patent_app_type] => utility [patent_app_number] => 16/647304 [patent_app_country] => US [patent_app_date] => 2018-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 6320 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16647304 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/647304
Method for manufacturing a semiconductor device and semiconductor device Aug 22, 2018 Issued
Array ( [id] => 13996647 [patent_doc_number] => 20190067481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => METHOD OF FORMING A FINFET HAVING A RELAXATION PREVENTION ANCHOR [patent_app_type] => utility [patent_app_number] => 16/047701 [patent_app_country] => US [patent_app_date] => 2018-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6448 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16047701 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/047701
Method of forming a FinFET having a relaxation prevention anchor Jul 26, 2018 Issued
Array ( [id] => 15200607 [patent_doc_number] => 10497808 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-03 [patent_title] => Method of making a CMOS semiconductor device using a stressed silicon-on-insulator (SOI) wafer [patent_app_type] => utility [patent_app_number] => 16/035458 [patent_app_country] => US [patent_app_date] => 2018-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 2492 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16035458 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/035458
Method of making a CMOS semiconductor device using a stressed silicon-on-insulator (SOI) wafer Jul 12, 2018 Issued
Array ( [id] => 13528691 [patent_doc_number] => 20180315888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-01 [patent_title] => LIGHT EMITTING DEVICE [patent_app_type] => utility [patent_app_number] => 16/028657 [patent_app_country] => US [patent_app_date] => 2018-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4430 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16028657 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/028657
Light emitting device Jul 5, 2018 Issued
Array ( [id] => 13598133 [patent_doc_number] => 20180350615 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-06 [patent_title] => METHODS OF PLASMA ETCHING AND PLASMA DICING [patent_app_type] => utility [patent_app_number] => 15/995184 [patent_app_country] => US [patent_app_date] => 2018-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4914 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15995184 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/995184
Methods of plasma etching and plasma dicing May 31, 2018 Issued
Array ( [id] => 15275021 [patent_doc_number] => 20190386245 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-19 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/334244 [patent_app_country] => US [patent_app_date] => 2018-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3709 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16334244 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/334244
Display device May 30, 2018 Issued
Array ( [id] => 14446975 [patent_doc_number] => 20190181361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-13 [patent_title] => FLEXIBLE SUBSTRATE AND DISPLAY DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 15/990041 [patent_app_country] => US [patent_app_date] => 2018-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6849 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15990041 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/990041
Flexible substrate and display device including the same May 24, 2018 Issued
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