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Jonathan Han

Examiner (ID: 3446)

Most Active Art Unit
2818
Art Unit(s)
2818
Total Applications
1536
Issued Applications
1244
Pending Applications
118
Abandoned Applications
212

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17833660 [patent_doc_number] => 20220270964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-25 [patent_title] => METHOD OF FORMING HIGH DENSITY, HIGH SHORTING MARGIN, AND LOW CAPACITANCE INTERCONNECTS BY ALTERNATING RECESSED TRENCHES [patent_app_type] => utility [patent_app_number] => 17/743365 [patent_app_country] => US [patent_app_date] => 2022-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8912 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17743365 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/743365
Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenches May 11, 2022 Issued
Array ( [id] => 19286064 [patent_doc_number] => 20240222542 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => PHOTODETECTOR APPARATUS AND METHOD OF DETECTING LIGHT [patent_app_type] => utility [patent_app_number] => 18/558464 [patent_app_country] => US [patent_app_date] => 2022-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7131 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18558464 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/558464
PHOTODETECTOR APPARATUS AND METHOD OF DETECTING LIGHT May 8, 2022 Pending
Array ( [id] => 18757535 [patent_doc_number] => 20230360998 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => POWER ELECTRONIC DEVICES AND METHODS OF PACKAGING POWER ELECTRONIC DEVICES TAILORED FOR TRANSIENT THERMAL MANAGEMENT [patent_app_type] => utility [patent_app_number] => 17/738962 [patent_app_country] => US [patent_app_date] => 2022-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4861 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17738962 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/738962
POWER ELECTRONIC DEVICES AND METHODS OF PACKAGING POWER ELECTRONIC DEVICES TAILORED FOR TRANSIENT THERMAL MANAGEMENT May 5, 2022 Pending
Array ( [id] => 17833626 [patent_doc_number] => 20220270930 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-25 [patent_title] => CATALYST INFLUENCED CHEMICAL ETCHING FOR FABRICATING THREE-DIMENSIONAL SRAM ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 17/735476 [patent_app_country] => US [patent_app_date] => 2022-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16171 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17735476 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/735476
Catalyst influenced chemical etching for fabricating three-dimensional SRAM architectures May 2, 2022 Issued
Array ( [id] => 17993395 [patent_doc_number] => 20220359432 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => SEMICONDUCTOR PACKAGE WITH A SCRATCH PROTECTION LAYER AND METHOD OF FABRICATION [patent_app_type] => utility [patent_app_number] => 17/734168 [patent_app_country] => US [patent_app_date] => 2022-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4215 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17734168 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/734168
SEMICONDUCTOR PACKAGE WITH A SCRATCH PROTECTION LAYER AND METHOD OF FABRICATION May 1, 2022 Pending
Array ( [id] => 20334421 [patent_doc_number] => 12464717 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Semiconductor memory device and a manufacturing method of the semiconductor memory device [patent_app_type] => utility [patent_app_number] => 17/731787 [patent_app_country] => US [patent_app_date] => 2022-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 3143 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17731787 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/731787
Semiconductor memory device and a manufacturing method of the semiconductor memory device Apr 27, 2022 Issued
Array ( [id] => 18782309 [patent_doc_number] => 11824076 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-21 [patent_title] => Semiconductor package including an image sensor chip and a method of fabricating the same [patent_app_type] => utility [patent_app_number] => 17/731022 [patent_app_country] => US [patent_app_date] => 2022-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 23 [patent_no_of_words] => 7867 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17731022 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/731022
Semiconductor package including an image sensor chip and a method of fabricating the same Apr 26, 2022 Issued
Array ( [id] => 17795688 [patent_doc_number] => 20220254780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-11 [patent_title] => METHOD (AND RELATED APPARATUS) FOR FORMING A SEMICONDUCTOR DEVICE WITH REDUCED SPACING BETWEEN NANOSTRUCTURE FIELD-EFFECT TRANSISTORS [patent_app_type] => utility [patent_app_number] => 17/729390 [patent_app_country] => US [patent_app_date] => 2022-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25609 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17729390 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/729390
Method (and related apparatus) for forming a semiconductor device with reduced spacing between nanostructure field-effect transistors Apr 25, 2022 Issued
Array ( [id] => 18264492 [patent_doc_number] => 20230085734 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => IMAGE SENSOR PACKAGE AND SYSTEM HAVING THE SAME [patent_app_type] => utility [patent_app_number] => 17/728275 [patent_app_country] => US [patent_app_date] => 2022-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14670 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17728275 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/728275
Image sensor package and system having the same Apr 24, 2022 Issued
Array ( [id] => 18068118 [patent_doc_number] => 20220399206 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-15 [patent_title] => METHOD FOR BUILDING CONDUCTIVE THROUGH-HOLE VIAS IN GLASS SUBSTRATES [patent_app_type] => utility [patent_app_number] => 17/724317 [patent_app_country] => US [patent_app_date] => 2022-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2197 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17724317 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/724317
METHOD FOR BUILDING CONDUCTIVE THROUGH-HOLE VIAS IN GLASS SUBSTRATES Apr 18, 2022 Abandoned
Array ( [id] => 17780270 [patent_doc_number] => 20220246620 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => DRAM DEVICE INCLUDING AN AIR GAP AND A SEALING LAYER [patent_app_type] => utility [patent_app_number] => 17/723218 [patent_app_country] => US [patent_app_date] => 2022-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7935 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17723218 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/723218
DRAM device including an air gap and a sealing layer Apr 17, 2022 Issued
Array ( [id] => 20259052 [patent_doc_number] => 12431416 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Chip package with integrated current control [patent_app_type] => utility [patent_app_number] => 17/718220 [patent_app_country] => US [patent_app_date] => 2022-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 2303 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17718220 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/718220
Chip package with integrated current control Apr 10, 2022 Issued
Array ( [id] => 17752916 [patent_doc_number] => 20220231121 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => ISOLATION REGIONS IN INTEGRATED CIRCUIT STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/714182 [patent_app_country] => US [patent_app_date] => 2022-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14662 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17714182 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/714182
Isolation regions in integrated circuit structures Apr 5, 2022 Issued
Array ( [id] => 17752857 [patent_doc_number] => 20220231062 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => IMAGING DEVICE, METHOD OF PRODUCING IMAGING DEVICE, IMAGING APPARATUS, AND ELECTRONIC APPARATUS [patent_app_type] => utility [patent_app_number] => 17/714698 [patent_app_country] => US [patent_app_date] => 2022-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15468 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17714698 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/714698
IMAGING DEVICE, METHOD OF PRODUCING IMAGING DEVICE, IMAGING APPARATUS, AND ELECTRONIC APPARATUS Apr 5, 2022 Abandoned
Array ( [id] => 19935108 [patent_doc_number] => 12308316 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-20 [patent_title] => Anti-fuse storage layout and circuit thereof, and anti-fuse memory and design method thereof [patent_app_type] => utility [patent_app_number] => 17/712067 [patent_app_country] => US [patent_app_date] => 2022-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3396 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17712067 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/712067
Anti-fuse storage layout and circuit thereof, and anti-fuse memory and design method thereof Apr 1, 2022 Issued
Array ( [id] => 17725125 [patent_doc_number] => 20220217847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-07 [patent_title] => Integrated Circuit Structure [patent_app_type] => utility [patent_app_number] => 17/706037 [patent_app_country] => US [patent_app_date] => 2022-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5358 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17706037 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/706037
Integrated circuit structure Mar 27, 2022 Issued
Array ( [id] => 18796899 [patent_doc_number] => 11830733 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-28 [patent_title] => Patterned nanochannel sacrificial layer for semiconductor substrate reuse [patent_app_type] => utility [patent_app_number] => 17/656762 [patent_app_country] => US [patent_app_date] => 2022-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3681 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17656762 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/656762
Patterned nanochannel sacrificial layer for semiconductor substrate reuse Mar 27, 2022 Issued
Array ( [id] => 18661308 [patent_doc_number] => 20230307321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => LINER-FREE THROUGH-SILICON-VIAS FORMED BY SELECTIVE METAL DEPOSITION [patent_app_type] => utility [patent_app_number] => 17/705458 [patent_app_country] => US [patent_app_date] => 2022-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2507 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17705458 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/705458
Liner-free through-silicon-vias formed by selective metal deposition Mar 27, 2022 Issued
Array ( [id] => 17917205 [patent_doc_number] => 20220319601 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => SELECTION GATE SEPARATION FOR 3D NAND [patent_app_type] => utility [patent_app_number] => 17/705744 [patent_app_country] => US [patent_app_date] => 2022-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8632 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17705744 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/705744
Selection gate separation for 3D NAND Mar 27, 2022 Issued
Array ( [id] => 19906477 [patent_doc_number] => 12283493 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-22 [patent_title] => Packaging structure radiating electromagnetic waves in horizontal direction and method making the same [patent_app_type] => utility [patent_app_number] => 17/704752 [patent_app_country] => US [patent_app_date] => 2022-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 0 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17704752 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/704752
Packaging structure radiating electromagnetic waves in horizontal direction and method making the same Mar 24, 2022 Issued
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