Search

Jonathan Han

Examiner (ID: 5679, Phone: (571)270-7546 , Office: P/2818 )

Most Active Art Unit
2818
Art Unit(s)
2818
Total Applications
1545
Issued Applications
1249
Pending Applications
122
Abandoned Applications
212

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20259052 [patent_doc_number] => 12431416 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Chip package with integrated current control [patent_app_type] => utility [patent_app_number] => 17/718220 [patent_app_country] => US [patent_app_date] => 2022-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 2303 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17718220 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/718220
Chip package with integrated current control Apr 10, 2022 Issued
Array ( [id] => 17752916 [patent_doc_number] => 20220231121 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => ISOLATION REGIONS IN INTEGRATED CIRCUIT STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/714182 [patent_app_country] => US [patent_app_date] => 2022-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14662 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17714182 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/714182
Isolation regions in integrated circuit structures Apr 5, 2022 Issued
Array ( [id] => 17752857 [patent_doc_number] => 20220231062 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => IMAGING DEVICE, METHOD OF PRODUCING IMAGING DEVICE, IMAGING APPARATUS, AND ELECTRONIC APPARATUS [patent_app_type] => utility [patent_app_number] => 17/714698 [patent_app_country] => US [patent_app_date] => 2022-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15468 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17714698 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/714698
IMAGING DEVICE, METHOD OF PRODUCING IMAGING DEVICE, IMAGING APPARATUS, AND ELECTRONIC APPARATUS Apr 5, 2022 Abandoned
Array ( [id] => 19935108 [patent_doc_number] => 12308316 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-20 [patent_title] => Anti-fuse storage layout and circuit thereof, and anti-fuse memory and design method thereof [patent_app_type] => utility [patent_app_number] => 17/712067 [patent_app_country] => US [patent_app_date] => 2022-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3396 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17712067 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/712067
Anti-fuse storage layout and circuit thereof, and anti-fuse memory and design method thereof Apr 1, 2022 Issued
Array ( [id] => 18661308 [patent_doc_number] => 20230307321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => LINER-FREE THROUGH-SILICON-VIAS FORMED BY SELECTIVE METAL DEPOSITION [patent_app_type] => utility [patent_app_number] => 17/705458 [patent_app_country] => US [patent_app_date] => 2022-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2507 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17705458 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/705458
Liner-free through-silicon-vias formed by selective metal deposition Mar 27, 2022 Issued
Array ( [id] => 17725125 [patent_doc_number] => 20220217847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-07 [patent_title] => Integrated Circuit Structure [patent_app_type] => utility [patent_app_number] => 17/706037 [patent_app_country] => US [patent_app_date] => 2022-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5358 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17706037 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/706037
Integrated circuit structure Mar 27, 2022 Issued
Array ( [id] => 17917205 [patent_doc_number] => 20220319601 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => SELECTION GATE SEPARATION FOR 3D NAND [patent_app_type] => utility [patent_app_number] => 17/705744 [patent_app_country] => US [patent_app_date] => 2022-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8632 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17705744 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/705744
Selection gate separation for 3D NAND Mar 27, 2022 Issued
Array ( [id] => 18796899 [patent_doc_number] => 11830733 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-28 [patent_title] => Patterned nanochannel sacrificial layer for semiconductor substrate reuse [patent_app_type] => utility [patent_app_number] => 17/656762 [patent_app_country] => US [patent_app_date] => 2022-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3681 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17656762 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/656762
Patterned nanochannel sacrificial layer for semiconductor substrate reuse Mar 27, 2022 Issued
Array ( [id] => 20553221 [patent_doc_number] => 12564035 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-24 [patent_title] => Airgaps used in backend memory structures [patent_app_type] => utility [patent_app_number] => 17/704410 [patent_app_country] => US [patent_app_date] => 2022-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 5705 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17704410 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/704410
Airgaps used in backend memory structures Mar 24, 2022 Issued
Array ( [id] => 19906477 [patent_doc_number] => 12283493 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-22 [patent_title] => Packaging structure radiating electromagnetic waves in horizontal direction and method making the same [patent_app_type] => utility [patent_app_number] => 17/704752 [patent_app_country] => US [patent_app_date] => 2022-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 0 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17704752 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/704752
Packaging structure radiating electromagnetic waves in horizontal direction and method making the same Mar 24, 2022 Issued
Array ( [id] => 17723525 [patent_doc_number] => 20220216247 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-07 [patent_title] => WAFER LEVEL LENS [patent_app_type] => utility [patent_app_number] => 17/703664 [patent_app_country] => US [patent_app_date] => 2022-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13797 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17703664 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/703664
Wafer level lens Mar 23, 2022 Issued
Array ( [id] => 18804452 [patent_doc_number] => 11837616 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-05 [patent_title] => Wafer level lens [patent_app_type] => utility [patent_app_number] => 17/703754 [patent_app_country] => US [patent_app_date] => 2022-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 13878 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17703754 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/703754
Wafer level lens Mar 23, 2022 Issued
Array ( [id] => 18661235 [patent_doc_number] => 20230307248 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH DAMASCENE STRUCTURE BY USING ETCH STOP LAYER [patent_app_type] => utility [patent_app_number] => 17/701927 [patent_app_country] => US [patent_app_date] => 2022-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9233 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17701927 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/701927
Method for fabricating semiconductor device with damascene structure by using etch stop layer Mar 22, 2022 Issued
Array ( [id] => 17723470 [patent_doc_number] => 20220216192 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-07 [patent_title] => SEMICONDUCTOR PACKAGES AND METHODS OF FORMING SAME [patent_app_type] => utility [patent_app_number] => 17/701083 [patent_app_country] => US [patent_app_date] => 2022-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17092 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17701083 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/701083
Semiconductor packages and methods of forming same Mar 21, 2022 Issued
Array ( [id] => 17886498 [patent_doc_number] => 20220301976 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => CHIP PACKAGING DEVICE AND CORRESPONDING MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 17/698749 [patent_app_country] => US [patent_app_date] => 2022-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4126 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17698749 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/698749
CHIP PACKAGING DEVICE AND CORRESPONDING MANUFACTURING METHOD Mar 17, 2022 Abandoned
Array ( [id] => 17993254 [patent_doc_number] => 20220359291 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/689000 [patent_app_country] => US [patent_app_date] => 2022-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4895 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17689000 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/689000
Semiconductor structure and method for manufacturing semiconductor structure Mar 7, 2022 Issued
Array ( [id] => 18112925 [patent_doc_number] => 20230005805 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 17/684534 [patent_app_country] => US [patent_app_date] => 2022-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14576 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17684534 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/684534
Semiconductor device and electronic device Mar 1, 2022 Issued
Array ( [id] => 17917781 [patent_doc_number] => 20220320177 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => METHOD FOR MANUFACTURING DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/683364 [patent_app_country] => US [patent_app_date] => 2022-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11446 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17683364 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/683364
Method for manufacturing display device Feb 28, 2022 Issued
Array ( [id] => 20346010 [patent_doc_number] => 12469745 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Conductive structures with bottom-less barriers and liners [patent_app_type] => utility [patent_app_number] => 17/652593 [patent_app_country] => US [patent_app_date] => 2022-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 4404 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17652593 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/652593
Conductive structures with bottom-less barriers and liners Feb 24, 2022 Issued
Array ( [id] => 20900465 [patent_doc_number] => 12707745 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-08-11 [patent_title] => Photodetection device and electronic apparatus [patent_app_type] => utility [patent_app_number] => 18/546252 [patent_app_country] => US [patent_app_date] => 2022-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8081 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18546252 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/546252
PHOTODETECTION DEVICE AND ELECTRONIC APPARATUS Feb 20, 2022 Pending
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