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Jonathan Han

Examiner (ID: 3446)

Most Active Art Unit
2818
Art Unit(s)
2818
Total Applications
1536
Issued Applications
1244
Pending Applications
118
Abandoned Applications
212

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14177781 [patent_doc_number] => 10262911 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-04-16 [patent_title] => Circuit for and method of testing bond connections between a first die and a second die [patent_app_type] => utility [patent_app_number] => 15/379258 [patent_app_country] => US [patent_app_date] => 2016-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 5900 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15379258 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/379258
Circuit for and method of testing bond connections between a first die and a second die Dec 13, 2016 Issued
Array ( [id] => 11997468 [patent_doc_number] => 20170301623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-19 [patent_title] => 'STACK OF LAYERS FOR PROTECTING AGAINST A PREMATURE BREAKDOWN OF INTERLINE POROUS DIELECTRICS WITHIN AN INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 15/379146 [patent_app_country] => US [patent_app_date] => 2016-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3869 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15379146 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/379146
Stack of layers for protecting against a premature breakdown of interline porous dielectrics within an integrated circuit Dec 13, 2016 Issued
Array ( [id] => 12918175 [patent_doc_number] => 20180197901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-12 [patent_title] => THIN FILM TRANSISTOR, DISPLAY SUBSTRATE AND DISPLAY PANEL HAVING THE SAME, AND FABRICATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/533109 [patent_app_country] => US [patent_app_date] => 2016-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13762 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15533109 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/533109
Thin film transistor, display substrate and display panel having the same, and fabricating method thereof Dec 11, 2016 Issued
Array ( [id] => 14125795 [patent_doc_number] => 10249763 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-02 [patent_title] => Array substrate, and display device, and fabrication methods [patent_app_type] => utility [patent_app_number] => 15/528215 [patent_app_country] => US [patent_app_date] => 2016-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 11207 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15528215 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/528215
Array substrate, and display device, and fabrication methods Dec 11, 2016 Issued
Array ( [id] => 12818860 [patent_doc_number] => 20180164792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-14 [patent_title] => AUTO DEFECT SCREENING USING ADAPTIVE MACHINE LEARNING IN SEMICONDUCTOR DEVICE MANUFACTURING FLOW [patent_app_type] => utility [patent_app_number] => 15/375186 [patent_app_country] => US [patent_app_date] => 2016-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4744 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15375186 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/375186
Auto defect screening using adaptive machine learning in semiconductor device manufacturing flow Dec 11, 2016 Issued
Array ( [id] => 11517671 [patent_doc_number] => 20170084745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'STRAINED SEMICONDUCTOR NANOWIRE' [patent_app_type] => utility [patent_app_number] => 15/365538 [patent_app_country] => US [patent_app_date] => 2016-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 8625 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15365538 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/365538
Strained semiconductor nanowire Nov 29, 2016 Issued
Array ( [id] => 12754225 [patent_doc_number] => 20180143242 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-24 [patent_title] => INTEGRATED CIRCUIT RELIABILITY ASSESSMENT APPARATUS AND METHOD [patent_app_type] => utility [patent_app_number] => 15/360899 [patent_app_country] => US [patent_app_date] => 2016-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11036 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15360899 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/360899
Integrated circuit reliability assessment apparatus and method Nov 22, 2016 Issued
Array ( [id] => 13862453 [patent_doc_number] => 10192954 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-29 [patent_title] => Junctionless nanowire transistor and manufacturing method for the same [patent_app_type] => utility [patent_app_number] => 15/314057 [patent_app_country] => US [patent_app_date] => 2016-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3320 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15314057 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/314057
Junctionless nanowire transistor and manufacturing method for the same Nov 15, 2016 Issued
Array ( [id] => 11625398 [patent_doc_number] => 20170135587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-18 [patent_title] => 'SYSTEMS AND METHODS FOR CONTROLLING AN INTERACTIVE WORKSTATION BASED ON BIOMETRIC INPUT' [patent_app_type] => utility [patent_app_number] => 15/349466 [patent_app_country] => US [patent_app_date] => 2016-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13478 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15349466 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/349466
Systems and methods for controlling an interactive workstation based on biometric input Nov 10, 2016 Issued
Array ( [id] => 15105609 [patent_doc_number] => 10474128 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-12 [patent_title] => Abnormality analysis system and analysis apparatus [patent_app_type] => utility [patent_app_number] => 15/349309 [patent_app_country] => US [patent_app_date] => 2016-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 12521 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15349309 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/349309
Abnormality analysis system and analysis apparatus Nov 10, 2016 Issued
Array ( [id] => 14150343 [patent_doc_number] => 10255555 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-09 [patent_title] => Generating quantum logic control sequences for quantum information processing hardware [patent_app_type] => utility [patent_app_number] => 15/348226 [patent_app_country] => US [patent_app_date] => 2016-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 10286 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15348226 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/348226
Generating quantum logic control sequences for quantum information processing hardware Nov 9, 2016 Issued
Array ( [id] => 11831972 [patent_doc_number] => 09728722 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-08 [patent_title] => 'Socket structure for three-dimensional memory' [patent_app_type] => utility [patent_app_number] => 15/342819 [patent_app_country] => US [patent_app_date] => 2016-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 5340 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15342819 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/342819
Socket structure for three-dimensional memory Nov 2, 2016 Issued
Array ( [id] => 12089008 [patent_doc_number] => 09842741 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-12 [patent_title] => 'Removal of semiconductor growth defects' [patent_app_type] => utility [patent_app_number] => 15/342794 [patent_app_country] => US [patent_app_date] => 2016-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 57 [patent_no_of_words] => 9561 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15342794 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/342794
Removal of semiconductor growth defects Nov 2, 2016 Issued
Array ( [id] => 11571932 [patent_doc_number] => 20170110576 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-20 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/290240 [patent_app_country] => US [patent_app_date] => 2016-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 17421 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15290240 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/290240
Semiconductor device and method for fabricating the same Oct 10, 2016 Issued
Array ( [id] => 12208546 [patent_doc_number] => 20180053772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-22 [patent_title] => 'MEMORY DEVICE HAVING INTERCHANGEABLE GATE/CHANNEL TRANSISTOR AND MANUFACTURING METHOD OF THE SAME' [patent_app_type] => utility [patent_app_number] => 15/290179 [patent_app_country] => US [patent_app_date] => 2016-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3238 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15290179 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/290179
Memory device having interchangeable gate/channel transistor and manufacturing method of the same Oct 10, 2016 Issued
Array ( [id] => 12095585 [patent_doc_number] => 20170352679 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-07 [patent_title] => 'THREE-DIMENSIONAL SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/290227 [patent_app_country] => US [patent_app_date] => 2016-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4644 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15290227 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/290227
Three-dimensional semiconductor device Oct 10, 2016 Issued
Array ( [id] => 12554244 [patent_doc_number] => 10014306 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-03 [patent_title] => Memory structure and manufacturing method for the same [patent_app_type] => utility [patent_app_number] => 15/290242 [patent_app_country] => US [patent_app_date] => 2016-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 45 [patent_no_of_words] => 4210 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15290242 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/290242
Memory structure and manufacturing method for the same Oct 10, 2016 Issued
Array ( [id] => 12953830 [patent_doc_number] => 09837421 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-05 [patent_title] => Semiconductor arrangement having capacitor separated from active region [patent_app_type] => utility [patent_app_number] => 15/289293 [patent_app_country] => US [patent_app_date] => 2016-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4660 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15289293 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/289293
Semiconductor arrangement having capacitor separated from active region Oct 9, 2016 Issued
Array ( [id] => 12012750 [patent_doc_number] => 09806073 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-31 [patent_title] => 'Electronic circuits including diode-connected bipolar junction transistors' [patent_app_type] => utility [patent_app_number] => 15/288326 [patent_app_country] => US [patent_app_date] => 2016-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4299 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15288326 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/288326
Electronic circuits including diode-connected bipolar junction transistors Oct 6, 2016 Issued
Array ( [id] => 14475869 [patent_doc_number] => 20190189582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => INDIUM SOLDER METALLURGY TO CONTROL ELECTRO-MIGRATION [patent_app_type] => utility [patent_app_number] => 16/328135 [patent_app_country] => US [patent_app_date] => 2016-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3352 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16328135 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/328135
Indium solder metallurgy to control electro-migration Sep 30, 2016 Issued
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