Search

Jonathan Han

Examiner (ID: 3833, Phone: (571)270-7546 , Office: P/2818 )

Most Active Art Unit
2818
Art Unit(s)
2818
Total Applications
1519
Issued Applications
1231
Pending Applications
120
Abandoned Applications
211

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11118147 [patent_doc_number] => 20160315121 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-27 [patent_title] => 'SOCKET STRUCTURE FOR THREE-DIMENSIONAL MEMORY' [patent_app_type] => utility [patent_app_number] => 14/695835 [patent_app_country] => US [patent_app_date] => 2015-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5301 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14695835 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/695835
Socket structure for three-dimensional memory Apr 23, 2015 Issued
Array ( [id] => 10118888 [patent_doc_number] => 09153780 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-06 [patent_title] => 'Semiconductor device and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 14/696059 [patent_app_country] => US [patent_app_date] => 2015-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 37 [patent_no_of_words] => 12515 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14696059 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/696059
Semiconductor device and method of fabricating the same Apr 23, 2015 Issued
Array ( [id] => 10826163 [patent_doc_number] => 20160172331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'SEMICONDUCTOR PACKAGE INCLUDING A PLURALITY OF STACKED CHIPS' [patent_app_type] => utility [patent_app_number] => 14/692429 [patent_app_country] => US [patent_app_date] => 2015-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7547 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14692429 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/692429
Semiconductor package including a plurality of stacked chips Apr 20, 2015 Issued
Array ( [id] => 10689632 [patent_doc_number] => 20160035778 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-04 [patent_title] => 'Thin Active Layer Fishbone Photodiode With A Shallow N+ Layer and Method of Manufacturing the Same' [patent_app_type] => utility [patent_app_number] => 14/685492 [patent_app_country] => US [patent_app_date] => 2015-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 15212 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14685492 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/685492
Thin Active Layer Fishbone Photodiode With A Shallow N+ Layer and Method of Manufacturing the Same Apr 12, 2015 Abandoned
Array ( [id] => 10329477 [patent_doc_number] => 20150214481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-30 [patent_title] => 'Memory Device Constructions, Memory Cell Forming Methods, and Semiconductor Construction Forming Methods' [patent_app_type] => utility [patent_app_number] => 14/680431 [patent_app_country] => US [patent_app_date] => 2015-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 13998 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14680431 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/680431
Semiconductor construction forming methods Apr 6, 2015 Issued
Array ( [id] => 10329340 [patent_doc_number] => 20150214344 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-30 [patent_title] => 'BIPOLAR JUNCTION TRANSISTORS WITH SELF-ALIGNED TERMINALS' [patent_app_type] => utility [patent_app_number] => 14/677303 [patent_app_country] => US [patent_app_date] => 2015-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7176 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14677303 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/677303
Bipolar junction transistors with self-aligned terminals Apr 1, 2015 Issued
Array ( [id] => 11904455 [patent_doc_number] => 09773897 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-26 [patent_title] => 'Multichannel devices with gate structures to increase breakdown voltage' [patent_app_type] => utility [patent_app_number] => 14/676285 [patent_app_country] => US [patent_app_date] => 2015-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3948 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14676285 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/676285
Multichannel devices with gate structures to increase breakdown voltage Mar 31, 2015 Issued
Array ( [id] => 10776024 [patent_doc_number] => 20160122179 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-05 [patent_title] => 'SENSOR PACKAGE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/673770 [patent_app_country] => US [patent_app_date] => 2015-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4568 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14673770 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/673770
SENSOR PACKAGE AND MANUFACTURING METHOD THEREOF Mar 29, 2015 Abandoned
Array ( [id] => 11292100 [patent_doc_number] => 20160342031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-24 [patent_title] => 'DISPLAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, DISPLAY PANEL AND DISPLAY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/785787 [patent_app_country] => US [patent_app_date] => 2015-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6795 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14785787 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/785787
Display substrate and manufacturing method thereof, display panel and display device Mar 26, 2015 Issued
Array ( [id] => 11637881 [patent_doc_number] => 09659865 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-23 [patent_title] => 'Field-effect transistor, method of manufacturing the same, and radio-frequency device' [patent_app_type] => utility [patent_app_number] => 14/897867 [patent_app_country] => US [patent_app_date] => 2015-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 44 [patent_no_of_words] => 11873 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14897867 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/897867
Field-effect transistor, method of manufacturing the same, and radio-frequency device Mar 24, 2015 Issued
Array ( [id] => 12228701 [patent_doc_number] => 09915942 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-13 [patent_title] => 'System and method for identifying significant and consumable-insensitive trace features' [patent_app_type] => utility [patent_app_number] => 14/663628 [patent_app_country] => US [patent_app_date] => 2015-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3590 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14663628 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/663628
System and method for identifying significant and consumable-insensitive trace features Mar 19, 2015 Issued
Array ( [id] => 10377524 [patent_doc_number] => 20150262531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-17 [patent_title] => 'ORGANIC THIN FILM TRANSISTOR MERGED WITH A LIGHT EMITTING DIODE USING AN ACCUMULATION LAYER AS ELECTRODE' [patent_app_type] => utility [patent_app_number] => 14/644220 [patent_app_country] => US [patent_app_date] => 2015-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7302 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14644220 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/644220
Organic thin film transistor merged with a light emitting diode using an accumulation layer as electrode Mar 10, 2015 Issued
Array ( [id] => 12102060 [patent_doc_number] => 09859159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-02 [patent_title] => 'Interconnection structure and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 14/644197 [patent_app_country] => US [patent_app_date] => 2015-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2554 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14644197 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/644197
Interconnection structure and manufacturing method thereof Mar 9, 2015 Issued
Array ( [id] => 10294578 [patent_doc_number] => 20150179577 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-25 [patent_title] => 'MULTILEVEL CONTACT TO A 3D MEMORY ARRAY AND METHOD OF MAKING THEREOF' [patent_app_type] => utility [patent_app_number] => 14/643211 [patent_app_country] => US [patent_app_date] => 2015-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 52 [patent_no_of_words] => 19085 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14643211 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/643211
Multilevel contact to a 3D memory array and method of making thereof Mar 9, 2015 Issued
Array ( [id] => 11346544 [patent_doc_number] => 09530960 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-27 [patent_title] => 'Memory device and manufacturing method therefor' [patent_app_type] => utility [patent_app_number] => 14/637680 [patent_app_country] => US [patent_app_date] => 2015-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 37 [patent_no_of_words] => 8426 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14637680 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/637680
Memory device and manufacturing method therefor Mar 3, 2015 Issued
Array ( [id] => 10294775 [patent_doc_number] => 20150179775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-25 [patent_title] => 'METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/626176 [patent_app_country] => US [patent_app_date] => 2015-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 16745 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14626176 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/626176
Method for manufacturing semiconductor device and semiconductor device Feb 18, 2015 Issued
Array ( [id] => 10277204 [patent_doc_number] => 20150162200 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-11 [patent_title] => 'SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SYSTEM OF PROCESSING SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 14/623495 [patent_app_country] => US [patent_app_date] => 2015-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 12145 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14623495 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/623495
Semiconductor device, method of manufacturing semiconductor device and system of processing substrate Feb 15, 2015 Issued
Array ( [id] => 11043495 [patent_doc_number] => 20160240451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'INTERCONNECT STRUCTURE FOR SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE INTERCONNECT STRUCTURE' [patent_app_type] => utility [patent_app_number] => 14/622484 [patent_app_country] => US [patent_app_date] => 2015-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6913 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14622484 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/622484
Interconnect structure for semiconductor package and method of fabricating the interconnect structure Feb 12, 2015 Issued
Array ( [id] => 10262868 [patent_doc_number] => 20150147865 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-28 [patent_title] => 'RESISTIVE-SWITCHING MEMORY ELEMENTS HAVING IMPROVED SWITCHING CHARACTERISTICS' [patent_app_type] => utility [patent_app_number] => 14/612897 [patent_app_country] => US [patent_app_date] => 2015-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 12645 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14612897 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/612897
Resistive-switching memory elements having improved switching characteristics Feb 2, 2015 Issued
Array ( [id] => 10259952 [patent_doc_number] => 20150144949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-28 [patent_title] => 'Semiconductor Device and Manufacturing Method Thereof' [patent_app_type] => utility [patent_app_number] => 14/607664 [patent_app_country] => US [patent_app_date] => 2015-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 11582 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14607664 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/607664
Semiconductor device and manufacturing method thereof Jan 27, 2015 Issued
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