Search

Jonathan Han

Examiner (ID: 5679, Phone: (571)270-7546 , Office: P/2818 )

Most Active Art Unit
2818
Art Unit(s)
2818
Total Applications
1545
Issued Applications
1249
Pending Applications
122
Abandoned Applications
212

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11265948 [patent_doc_number] => 09490251 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-08 [patent_title] => 'Diode-connected bipolar junction transistors and electronic circuits including the same' [patent_app_type] => utility [patent_app_number] => 14/322775 [patent_app_country] => US [patent_app_date] => 2014-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4366 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14322775 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/322775
Diode-connected bipolar junction transistors and electronic circuits including the same Jul 1, 2014 Issued
Array ( [id] => 11538057 [patent_doc_number] => 09612459 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-04 [patent_title] => 'Silicon optical modulator using asymmetric shallow waveguide and the method to make the same' [patent_app_type] => utility [patent_app_number] => 14/321376 [patent_app_country] => US [patent_app_date] => 2014-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 3276 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 308 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14321376 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/321376
Silicon optical modulator using asymmetric shallow waveguide and the method to make the same Jun 30, 2014 Issued
Array ( [id] => 10659681 [patent_doc_number] => 20160005824 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-07 [patent_title] => 'CONTACT STRUCTURES AND METHODS OF FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/321366 [patent_app_country] => US [patent_app_date] => 2014-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5599 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14321366 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/321366
Contact structures and methods of forming the same Jun 30, 2014 Issued
Array ( [id] => 11201174 [patent_doc_number] => 09431395 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-30 [patent_title] => 'Protection of semiconductor-oxide-containing gate dielectric during replacement gate formation' [patent_app_type] => utility [patent_app_number] => 14/320760 [patent_app_country] => US [patent_app_date] => 2014-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 112 [patent_no_of_words] => 13379 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14320760 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/320760
Protection of semiconductor-oxide-containing gate dielectric during replacement gate formation Jun 30, 2014 Issued
Array ( [id] => 10315005 [patent_doc_number] => 20150200008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-16 [patent_title] => 'SEMICONDUCTOR PACKAGE AND ELECTRONIC APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/321166 [patent_app_country] => US [patent_app_date] => 2014-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 13458 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14321166 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/321166
SEMICONDUCTOR PACKAGE AND ELECTRONIC APPARATUS Jun 30, 2014 Abandoned
Array ( [id] => 10321582 [patent_doc_number] => 20150206585 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-23 [patent_title] => 'ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/321719 [patent_app_country] => US [patent_app_date] => 2014-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10390 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14321719 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/321719
Electronic device and method for fabricating the same Jun 30, 2014 Issued
Array ( [id] => 10659561 [patent_doc_number] => 20160005705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-07 [patent_title] => 'Structure and Method of Batch-Packaging Low Pin Count Embedded Semiconductor Chips' [patent_app_type] => utility [patent_app_number] => 14/320825 [patent_app_country] => US [patent_app_date] => 2014-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2907 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14320825 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/320825
Structure and Method of Batch-Packaging Low Pin Count Embedded Semiconductor Chips Jun 30, 2014 Abandoned
Array ( [id] => 11233692 [patent_doc_number] => 09460926 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-04 [patent_title] => 'Forming JFET and LDMOS transistor in monolithic power integrated circuit using deep diffusion regions' [patent_app_type] => utility [patent_app_number] => 14/320434 [patent_app_country] => US [patent_app_date] => 2014-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3886 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 332 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14320434 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/320434
Forming JFET and LDMOS transistor in monolithic power integrated circuit using deep diffusion regions Jun 29, 2014 Issued
Array ( [id] => 10495609 [patent_doc_number] => 20150380631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'Electronic Circuitry Having Superconducting Tunnel Junctions with Functional Electromagnetic-Responsive Tunneling Regions' [patent_app_type] => utility [patent_app_number] => 14/319112 [patent_app_country] => US [patent_app_date] => 2014-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3365 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14319112 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/319112
Electronic circuitry having superconducting tunnel junctions with functional electromagnetic-responsive tunneling regions Jun 29, 2014 Issued
Array ( [id] => 10093225 [patent_doc_number] => 09130057 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-09-08 [patent_title] => 'Hybrid dicing process using a blade and laser' [patent_app_type] => utility [patent_app_number] => 14/320405 [patent_app_country] => US [patent_app_date] => 2014-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 23 [patent_no_of_words] => 5674 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14320405 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/320405
Hybrid dicing process using a blade and laser Jun 29, 2014 Issued
Array ( [id] => 10912320 [patent_doc_number] => 20140315337 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-23 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/320366 [patent_app_country] => US [patent_app_date] => 2014-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4776 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14320366 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/320366
Semiconductor device and method for manufacturing the same Jun 29, 2014 Issued
Array ( [id] => 10492932 [patent_doc_number] => 20150377954 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'Method for Testing Semiconductor Dies and a Test Apparatus' [patent_app_type] => utility [patent_app_number] => 14/319268 [patent_app_country] => US [patent_app_date] => 2014-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2839 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14319268 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/319268
Method for testing semiconductor dies and a test apparatus Jun 29, 2014 Issued
Array ( [id] => 10329179 [patent_doc_number] => 20150214183 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-30 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/319315 [patent_app_country] => US [patent_app_date] => 2014-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4519 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14319315 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/319315
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME Jun 29, 2014 Abandoned
Array ( [id] => 11787654 [patent_doc_number] => 09397118 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-19 [patent_title] => 'Thin-film ambipolar logic' [patent_app_type] => utility [patent_app_number] => 14/318846 [patent_app_country] => US [patent_app_date] => 2014-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7095 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14318846 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/318846
Thin-film ambipolar logic Jun 29, 2014 Issued
Array ( [id] => 10583806 [patent_doc_number] => 09305932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-05 [patent_title] => 'Methods of making three dimensional NAND devices' [patent_app_type] => utility [patent_app_number] => 14/319283 [patent_app_country] => US [patent_app_date] => 2014-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 41 [patent_no_of_words] => 6570 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14319283 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/319283
Methods of making three dimensional NAND devices Jun 29, 2014 Issued
Array ( [id] => 10495383 [patent_doc_number] => 20150380405 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'REMOVAL OF SEMICONDUCTOR GROWTH DEFECTS' [patent_app_type] => utility [patent_app_number] => 14/318822 [patent_app_country] => US [patent_app_date] => 2014-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 9561 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14318822 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/318822
Removal of semiconductor growth defects Jun 29, 2014 Issued
Array ( [id] => 10652110 [patent_doc_number] => 09368373 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-14 [patent_title] => 'Method of joining semiconductor substrate' [patent_app_type] => utility [patent_app_number] => 14/319324 [patent_app_country] => US [patent_app_date] => 2014-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2291 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14319324 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/319324
Method of joining semiconductor substrate Jun 29, 2014 Issued
Array ( [id] => 10495402 [patent_doc_number] => 20150380424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'METHODS OF MAKING THREE DIMENSIONAL NAND DEVICES' [patent_app_type] => utility [patent_app_number] => 14/319591 [patent_app_country] => US [patent_app_date] => 2014-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6062 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14319591 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/319591
Methods of making three dimensional NAND devices Jun 29, 2014 Issued
Array ( [id] => 10495461 [patent_doc_number] => 20150380483 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'COMPACT GUARD RING STRUCTURE FOR CMOS INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 14/320462 [patent_app_country] => US [patent_app_date] => 2014-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3288 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14320462 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/320462
Compact guard ring structure for CMOS integrated circuits Jun 29, 2014 Issued
Array ( [id] => 10493354 [patent_doc_number] => 20150378375 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'Cascode Circuit' [patent_app_type] => utility [patent_app_number] => 14/318820 [patent_app_country] => US [patent_app_date] => 2014-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8497 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14318820 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/318820
Cascode circuit Jun 29, 2014 Issued
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