Search

Jonathan Han

Examiner (ID: 5679, Phone: (571)270-7546 , Office: P/2818 )

Most Active Art Unit
2818
Art Unit(s)
2818
Total Applications
1545
Issued Applications
1249
Pending Applications
122
Abandoned Applications
212

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5171931 [patent_doc_number] => 20070072364 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'Method for fabricating transistor gate structures and gate dielectrics thereof' [patent_app_type] => utility [patent_app_number] => 11/549375 [patent_app_country] => US [patent_app_date] => 2006-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6406 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20070072364.pdf [firstpage_image] =>[orig_patent_app_number] => 11549375 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/549375
Method for fabricating transistor gate structures and gate dielectrics thereof Oct 12, 2006 Abandoned
Array ( [id] => 4692827 [patent_doc_number] => 20080085598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-10 [patent_title] => 'METHOD OF PATTERNING CONTACT HOLES' [patent_app_type] => utility [patent_app_number] => 11/538475 [patent_app_country] => US [patent_app_date] => 2006-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1912 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20080085598.pdf [firstpage_image] =>[orig_patent_app_number] => 11538475 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/538475
METHOD OF PATTERNING CONTACT HOLES Oct 3, 2006 Abandoned
Array ( [id] => 5092911 [patent_doc_number] => 20070114520 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-24 [patent_title] => 'Radiation emitting device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/516446 [patent_app_country] => US [patent_app_date] => 2006-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4244 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0114/20070114520.pdf [firstpage_image] =>[orig_patent_app_number] => 11516446 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/516446
Radiation emitting device and method of manufacturing the same Sep 4, 2006 Abandoned
Array ( [id] => 9552852 [patent_doc_number] => 08759903 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-06-24 [patent_title] => 'Method of fabricating total dose hard and thermal neutron hard integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/469757 [patent_app_country] => US [patent_app_date] => 2006-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4712 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11469757 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/469757
Method of fabricating total dose hard and thermal neutron hard integrated circuits Aug 31, 2006 Issued
Array ( [id] => 4667071 [patent_doc_number] => 20080042131 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-21 [patent_title] => 'System for displaying images including thin film transistor device and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/504490 [patent_app_country] => US [patent_app_date] => 2006-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2626 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20080042131.pdf [firstpage_image] =>[orig_patent_app_number] => 11504490 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/504490
System for displaying images including thin film transistor device and method for fabricating the same Aug 14, 2006 Abandoned
Array ( [id] => 8774308 [patent_doc_number] => 08428278 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-23 [patent_title] => 'Improvements to systems for acoustic diffusion' [patent_app_type] => utility [patent_app_number] => 12/376837 [patent_app_country] => US [patent_app_date] => 2006-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5523 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12376837 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/376837
Improvements to systems for acoustic diffusion Aug 9, 2006 Issued
Array ( [id] => 4859767 [patent_doc_number] => 20080268617 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-30 [patent_title] => 'METHODS FOR SUBSTRATE SURFACE CLEANING SUITABLE FOR FABRICATING SILICON-ON-INSULATOR STRUCTURES' [patent_app_type] => utility [patent_app_number] => 11/463429 [patent_app_country] => US [patent_app_date] => 2006-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4489 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20080268617.pdf [firstpage_image] =>[orig_patent_app_number] => 11463429 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/463429
METHODS FOR SUBSTRATE SURFACE CLEANING SUITABLE FOR FABRICATING SILICON-ON-INSULATOR STRUCTURES Aug 8, 2006 Abandoned
Array ( [id] => 24521 [patent_doc_number] => 07800879 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-21 [patent_title] => 'On-chip sensor array for temperature management in integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/460459 [patent_app_country] => US [patent_app_date] => 2006-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3573 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/800/07800879.pdf [firstpage_image] =>[orig_patent_app_number] => 11460459 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/460459
On-chip sensor array for temperature management in integrated circuits Jul 26, 2006 Issued
Array ( [id] => 6278855 [patent_doc_number] => 20100155382 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-24 [patent_title] => 'Method for Machining Valve Mechanism Component Member' [patent_app_type] => utility [patent_app_number] => 11/989953 [patent_app_country] => US [patent_app_date] => 2006-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6288 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20100155382.pdf [firstpage_image] =>[orig_patent_app_number] => 11989953 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/989953
Method for Machining Valve Mechanism Component Member Jul 5, 2006 Abandoned
Array ( [id] => 5228287 [patent_doc_number] => 20070290394 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-20 [patent_title] => 'METHOD AND STRUCTURE FOR FORMING SELF-PLANARIZING WIRING LAYERS IN MULTILEVEL ELECTRONIC DEVICES' [patent_app_type] => utility [patent_app_number] => 11/425210 [patent_app_country] => US [patent_app_date] => 2006-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1981 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0290/20070290394.pdf [firstpage_image] =>[orig_patent_app_number] => 11425210 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/425210
METHOD AND STRUCTURE FOR FORMING SELF-PLANARIZING WIRING LAYERS IN MULTILEVEL ELECTRONIC DEVICES Jun 19, 2006 Abandoned
Array ( [id] => 6216153 [patent_doc_number] => 20100052177 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-04 [patent_title] => 'METHOD FOR MANUFACTURING A CROSSBAR CIRCUIT DEVICE' [patent_app_type] => utility [patent_app_number] => 11/916122 [patent_app_country] => US [patent_app_date] => 2006-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5925 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20100052177.pdf [firstpage_image] =>[orig_patent_app_number] => 11916122 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/916122
METHOD FOR MANUFACTURING A CROSSBAR CIRCUIT DEVICE May 23, 2006 Abandoned
Array ( [id] => 5330733 [patent_doc_number] => 20090111210 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-30 [patent_title] => 'Method for Organic Semiconductor Material Thin-Film Formation and Process for Producing Organic Thin Film Transistor' [patent_app_type] => utility [patent_app_number] => 11/922466 [patent_app_country] => US [patent_app_date] => 2006-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 10484 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20090111210.pdf [firstpage_image] =>[orig_patent_app_number] => 11922466 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/922466
Method for Organic Semiconductor Material Thin-Film Formation and Process for Producing Organic Thin Film Transistor May 22, 2006 Abandoned
Array ( [id] => 9503372 [patent_doc_number] => 08741685 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-03 [patent_title] => 'Sulfurization and selenization of electrodeposited CIGS films by thermal annealing' [patent_app_type] => utility [patent_app_number] => 11/915576 [patent_app_country] => US [patent_app_date] => 2006-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 5981 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11915576 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/915576
Sulfurization and selenization of electrodeposited CIGS films by thermal annealing May 18, 2006 Issued
Array ( [id] => 5364838 [patent_doc_number] => 20090302397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-10 [patent_title] => 'Field-Effect Transistor' [patent_app_type] => utility [patent_app_number] => 11/920864 [patent_app_country] => US [patent_app_date] => 2006-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1943 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0302/20090302397.pdf [firstpage_image] =>[orig_patent_app_number] => 11920864 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/920864
Field-Effect Transistor Apr 4, 2006 Abandoned
Array ( [id] => 9704592 [patent_doc_number] => 08829661 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-09 [patent_title] => 'Warp compensated package and method' [patent_app_type] => utility [patent_app_number] => 11/372666 [patent_app_country] => US [patent_app_date] => 2006-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 8073 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11372666 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/372666
Warp compensated package and method Mar 9, 2006 Issued
Array ( [id] => 42684 [patent_doc_number] => 07781350 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-24 [patent_title] => 'Method and system for controllable deposition of nanoparticles on a substrate' [patent_app_type] => utility [patent_app_number] => 11/360440 [patent_app_country] => US [patent_app_date] => 2006-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 54 [patent_no_of_words] => 10249 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/781/07781350.pdf [firstpage_image] =>[orig_patent_app_number] => 11360440 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/360440
Method and system for controllable deposition of nanoparticles on a substrate Feb 23, 2006 Issued
Array ( [id] => 5262285 [patent_doc_number] => 20090114970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-07 [patent_title] => 'EMBEDDED DRAM WITH INCREASED CAPACITANCE AND METHOD OF MANUFACTURING SAME' [patent_app_type] => utility [patent_app_number] => 11/816706 [patent_app_country] => US [patent_app_date] => 2006-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2712 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0114/20090114970.pdf [firstpage_image] =>[orig_patent_app_number] => 11816706 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/816706
EMBEDDED DRAM WITH INCREASED CAPACITANCE AND METHOD OF MANUFACTURING SAME Feb 14, 2006 Abandoned
Array ( [id] => 5253599 [patent_doc_number] => 20070135055 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-14 [patent_title] => 'Combination quad flat no-lead and thin small outline package' [patent_app_type] => utility [patent_app_number] => 11/301713 [patent_app_country] => US [patent_app_date] => 2005-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1326 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0135/20070135055.pdf [firstpage_image] =>[orig_patent_app_number] => 11301713 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/301713
Combination quad flat no-lead and thin small outline package Dec 12, 2005 Abandoned
Array ( [id] => 4708032 [patent_doc_number] => 20080296558 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-04 [patent_title] => 'Method of Synthesizing Y-Junction Single-Walled Carbon Nanotubes and Products Formed Thereby' [patent_app_type] => utility [patent_app_number] => 11/718975 [patent_app_country] => US [patent_app_date] => 2005-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6043 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0296/20080296558.pdf [firstpage_image] =>[orig_patent_app_number] => 11718975 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/718975
Method of Synthesizing Y-Junction Single-Walled Carbon Nanotubes and Products Formed Thereby Nov 13, 2005 Abandoned
Array ( [id] => 4849607 [patent_doc_number] => 20080315349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-25 [patent_title] => 'Method for Manufacturing Bonded Wafer and Bonded Wafer' [patent_app_type] => utility [patent_app_number] => 11/883816 [patent_app_country] => US [patent_app_date] => 2005-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6980 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0315/20080315349.pdf [firstpage_image] =>[orig_patent_app_number] => 11883816 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/883816
Method for Manufacturing Bonded Wafer and Bonded Wafer Nov 1, 2005 Abandoned
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