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Jonathan Peter Masinick

Examiner (ID: 1807, Phone: (571)270-3060 , Office: P/3679 )

Most Active Art Unit
3678
Art Unit(s)
3679, 3678
Total Applications
1028
Issued Applications
725
Pending Applications
78
Abandoned Applications
251

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6958654 [patent_doc_number] => 20050215024 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-29 [patent_title] => 'Methods for forming super-steep diffusion region profiles in MOS devices and resulting semiconductor topographies' [patent_app_type] => utility [patent_app_number] => 11/069501 [patent_app_country] => US [patent_app_date] => 2005-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10687 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0215/20050215024.pdf [firstpage_image] =>[orig_patent_app_number] => 11069501 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/069501
Methods for forming super-steep diffusion region profiles in MOS devices and resulting semiconductor topographies Feb 28, 2005 Issued
Array ( [id] => 7116771 [patent_doc_number] => 20050070072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-31 [patent_title] => 'Method for processing wafer' [patent_app_type] => utility [patent_app_number] => 10/947242 [patent_app_country] => US [patent_app_date] => 2004-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3519 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20050070072.pdf [firstpage_image] =>[orig_patent_app_number] => 10947242 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/947242
Method for processing wafer Sep 22, 2004 Issued
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