Jonathan R Horner
Examiner (ID: 580, Phone: (571)270-7358 , Office: P/2694 )
Most Active Art Unit | 2694 |
Art Unit(s) | OITP, OPIM, 2629, 2694 |
Total Applications | 316 |
Issued Applications | 126 |
Pending Applications | 1 |
Abandoned Applications | 189 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 7801735
[patent_doc_number] => 08130010
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-03-06
[patent_title] => 'Signal lines with internal and external termination'
[patent_app_type] => utility
[patent_app_number] => 13/022539
[patent_app_country] => US
[patent_app_date] => 2011-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3244
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 17
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/130/08130010.pdf
[firstpage_image] =>[orig_patent_app_number] => 13022539
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/022539 | Signal lines with internal and external termination | Feb 6, 2011 | Issued |
Array
(
[id] => 4615336
[patent_doc_number] => 07990783
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2011-08-02
[patent_title] => 'Postamble timing for DDR memories'
[patent_app_type] => utility
[patent_app_number] => 13/004136
[patent_app_country] => US
[patent_app_date] => 2011-01-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 13
[patent_no_of_words] => 5767
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/990/07990783.pdf
[firstpage_image] =>[orig_patent_app_number] => 13004136
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/004136 | Postamble timing for DDR memories | Jan 10, 2011 | Issued |
Array
(
[id] => 6645100
[patent_doc_number] => 20100313174
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-12-09
[patent_title] => 'Systems and Methods for Improving the PN Ratio of a Logic Gate by Adding a Non-Switching Transistor'
[patent_app_type] => utility
[patent_app_number] => 12/858985
[patent_app_country] => US
[patent_app_date] => 2010-08-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3992
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0313/20100313174.pdf
[firstpage_image] =>[orig_patent_app_number] => 12858985
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/858985 | Systems and Methods for Improving the PN Ratio of a Logic Gate by Adding a Non-Switching Transistor | Aug 17, 2010 | Abandoned |
Array
(
[id] => 4477911
[patent_doc_number] => 07868646
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2011-01-11
[patent_title] => 'Soft error upset hardened integrated circuit systems and methods'
[patent_app_type] => utility
[patent_app_number] => 12/818544
[patent_app_country] => US
[patent_app_date] => 2010-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 19
[patent_no_of_words] => 9106
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/868/07868646.pdf
[firstpage_image] =>[orig_patent_app_number] => 12818544
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/818544 | Soft error upset hardened integrated circuit systems and methods | Jun 17, 2010 | Issued |
Array
(
[id] => 4481257
[patent_doc_number] => 07869388
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-01-11
[patent_title] => 'Class-B transmitter and replica transmitter for gigabit ethernet applications'
[patent_app_type] => utility
[patent_app_number] => 12/800959
[patent_app_country] => US
[patent_app_date] => 2010-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 3255
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 177
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/869/07869388.pdf
[firstpage_image] =>[orig_patent_app_number] => 12800959
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/800959 | Class-B transmitter and replica transmitter for gigabit ethernet applications | May 25, 2010 | Issued |
Array
(
[id] => 7486473
[patent_doc_number] => 20110250860
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-10-13
[patent_title] => 'RECEIVER AND METHOD FOR DYNAMICALLY ADJUSTING SENSITIVITY OF RECEIVER'
[patent_app_type] => utility
[patent_app_number] => 12/759355
[patent_app_country] => US
[patent_app_date] => 2010-04-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5194
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0250/20110250860.pdf
[firstpage_image] =>[orig_patent_app_number] => 12759355
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/759355 | Receiver and method for dynamically adjusting sensitivity of receiver | Apr 12, 2010 | Issued |
Array
(
[id] => 7480774
[patent_doc_number] => 20110248745
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-10-13
[patent_title] => 'STAGED PREDRIVER FOR HIGH SPEED DIFFERENTIAL TRANSMITTER'
[patent_app_type] => utility
[patent_app_number] => 12/755909
[patent_app_country] => US
[patent_app_date] => 2010-04-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7917
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0248/20110248745.pdf
[firstpage_image] =>[orig_patent_app_number] => 12755909
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/755909 | Staged predriver for high speed differential transmitter | Apr 6, 2010 | Issued |
Array
(
[id] => 6414332
[patent_doc_number] => 20100141297
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-06-10
[patent_title] => 'Configuration of Reconfigurable Interconnect Portions'
[patent_app_type] => utility
[patent_app_number] => 12/706831
[patent_app_country] => US
[patent_app_date] => 2010-02-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 7933
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0141/20100141297.pdf
[firstpage_image] =>[orig_patent_app_number] => 12706831
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/706831 | Configuration of reconfigurable interconnect portions | Feb 16, 2010 | Issued |
Array
(
[id] => 7551330
[patent_doc_number] => 08063664
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-11-22
[patent_title] => 'Distributed supply current switch circuits for enabling individual power domains'
[patent_app_type] => utility
[patent_app_number] => 12/642651
[patent_app_country] => US
[patent_app_date] => 2009-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 20
[patent_no_of_words] => 11386
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 206
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/063/08063664.pdf
[firstpage_image] =>[orig_patent_app_number] => 12642651
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/642651 | Distributed supply current switch circuits for enabling individual power domains | Dec 17, 2009 | Issued |
Array
(
[id] => 7556058
[patent_doc_number] => 08067961
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-11-29
[patent_title] => 'Level conversion circuit for converting voltage amplitude of signal'
[patent_app_type] => utility
[patent_app_number] => 12/634608
[patent_app_country] => US
[patent_app_date] => 2009-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 11
[patent_no_of_words] => 7924
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 280
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/067/08067961.pdf
[firstpage_image] =>[orig_patent_app_number] => 12634608
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/634608 | Level conversion circuit for converting voltage amplitude of signal | Dec 8, 2009 | Issued |
Array
(
[id] => 6121672
[patent_doc_number] => 20110084733
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-04-14
[patent_title] => 'DRIVING CIRCUIT WITH SLEW-RATE ENHANCEMENT CIRCUIT'
[patent_app_type] => utility
[patent_app_number] => 12/577851
[patent_app_country] => US
[patent_app_date] => 2009-10-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2560
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0084/20110084733.pdf
[firstpage_image] =>[orig_patent_app_number] => 12577851
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/577851 | Driving circuit with slew-rate enhancement circuit | Oct 12, 2009 | Issued |
Array
(
[id] => 6462069
[patent_doc_number] => 20100090720
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-04-15
[patent_title] => 'FLEXIBLE PARALLEL/SERIAL RECONFIGURABLE ARRAY CONFIGURATION SCHEME'
[patent_app_type] => utility
[patent_app_number] => 12/576040
[patent_app_country] => US
[patent_app_date] => 2009-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 2334
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0090/20100090720.pdf
[firstpage_image] =>[orig_patent_app_number] => 12576040
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/576040 | Flexible parallel/serial reconfigurable array configuration scheme | Oct 7, 2009 | Issued |
Array
(
[id] => 6265342
[patent_doc_number] => 20100253392
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-10-07
[patent_title] => 'I/O BUFFER WITH TWICE THE SUPPLY VOLTAGE TOLERANCE USING NORMAL SUPPLY VOLTAGE DEVICES'
[patent_app_type] => utility
[patent_app_number] => 12/575787
[patent_app_country] => US
[patent_app_date] => 2009-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4572
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0253/20100253392.pdf
[firstpage_image] =>[orig_patent_app_number] => 12575787
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/575787 | I/O buffer with twice the supply voltage tolerance using normal supply voltage devices | Oct 7, 2009 | Issued |
Array
(
[id] => 6029969
[patent_doc_number] => 20110080973
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-04-07
[patent_title] => 'COMMON MODE CANCELLATION IN DIFFERENTIAL NETWORKS'
[patent_app_type] => utility
[patent_app_number] => 12/574923
[patent_app_country] => US
[patent_app_date] => 2009-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4211
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0080/20110080973.pdf
[firstpage_image] =>[orig_patent_app_number] => 12574923
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/574923 | Common mode cancellation in differential networks | Oct 6, 2009 | Issued |
Array
(
[id] => 6361594
[patent_doc_number] => 20100079168
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-04-01
[patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT AND LAYOUT METHOD'
[patent_app_type] => utility
[patent_app_number] => 12/562780
[patent_app_country] => US
[patent_app_date] => 2009-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 5970
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0079/20100079168.pdf
[firstpage_image] =>[orig_patent_app_number] => 12562780
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/562780 | SEMICONDUCTOR INTEGRATED CIRCUIT AND LAYOUT METHOD | Sep 17, 2009 | Abandoned |
Array
(
[id] => 6355265
[patent_doc_number] => 20100073023
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-03-25
[patent_title] => 'SIGNAL LINES WITH INTERNAL AND EXTERNAL TERMINATION'
[patent_app_type] => utility
[patent_app_number] => 12/555886
[patent_app_country] => US
[patent_app_date] => 2009-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3183
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0073/20100073023.pdf
[firstpage_image] =>[orig_patent_app_number] => 12555886
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/555886 | Signal lines with internal and external termination | Sep 8, 2009 | Issued |
Array
(
[id] => 6006505
[patent_doc_number] => 20110058641
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-03-10
[patent_title] => 'FAST DYNAMIC REGISTER'
[patent_app_type] => utility
[patent_app_number] => 12/555999
[patent_app_country] => US
[patent_app_date] => 2009-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6608
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0058/20110058641.pdf
[firstpage_image] =>[orig_patent_app_number] => 12555999
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/555999 | Fast dynamic register | Sep 8, 2009 | Issued |
Array
(
[id] => 6068419
[patent_doc_number] => 20110043268
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-02-24
[patent_title] => 'LEVEL SHIFTER WITH NATIVE DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/546276
[patent_app_country] => US
[patent_app_date] => 2009-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2703
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0043/20110043268.pdf
[firstpage_image] =>[orig_patent_app_number] => 12546276
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/546276 | LEVEL SHIFTER WITH NATIVE DEVICE | Aug 23, 2009 | Abandoned |
Array
(
[id] => 143583
[patent_doc_number] => 07692513
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-04-06
[patent_title] => 'Acoustic surface wave filter module and method of manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 12/462385
[patent_app_country] => US
[patent_app_date] => 2009-08-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 14
[patent_no_of_words] => 4220
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 366
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/692/07692513.pdf
[firstpage_image] =>[orig_patent_app_number] => 12462385
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/462385 | Acoustic surface wave filter module and method of manufacturing the same | Aug 2, 2009 | Issued |
Array
(
[id] => 5556071
[patent_doc_number] => 20090267648
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-10-29
[patent_title] => 'Apparatus for configuring I/O signal levels of interfacing logic circuits'
[patent_app_type] => utility
[patent_app_number] => 12/458204
[patent_app_country] => US
[patent_app_date] => 2009-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2264
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0267/20090267648.pdf
[firstpage_image] =>[orig_patent_app_number] => 12458204
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/458204 | Apparatus for configuring I/O signal levels of interfacing logic circuits | Jul 1, 2009 | Issued |