Jonathan R Horner

Array ( [id] => 5519098 [patent_doc_number] => 20090027079 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-29 [patent_title] => 'Method and Apparatus for Implementing Complex Logic Within a Memory Array' [patent_app_type] => utility [patent_app_number] => 12/250917 [patent_app_country] => US [patent_app_date] => 2008-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5069 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20090027079.pdf [firstpage_image] =>[orig_patent_app_number] => 12250917 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 35072 [patent_doc_number] => 07786758 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-31 [patent_title] => 'Asynchronous clock gate with glitch protection' [patent_app_type] => utility [patent_app_number] => 12/248268 [patent_app_country] => US [patent_app_date] => 2008-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3642 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/786/07786758.pdf [firstpage_image] =>[orig_patent_app_number] => 12248268 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6344043 [patent_doc_number] => 20100085078 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-08 [patent_title] => 'Digital Logic Voltage Level Shifter' [patent_app_type] => utility [patent_app_number] => 12/247000 [patent_app_country] => US [patent_app_date] => 2008-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3064 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20100085078.pdf [firstpage_image] =>[orig_patent_app_number] => 12247000 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5439774 [patent_doc_number] => 20090091413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-09 [patent_title] => 'SIGNAL TRANSFER CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/245081 [patent_app_country] => US [patent_app_date] => 2008-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 17201 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20090091413.pdf [firstpage_image] =>[orig_patent_app_number] => 12245081 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 68952 [patent_doc_number] => 07761714 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-20 [patent_title] => 'Integrated circuit and method for preventing an unauthorized access to a digital value' [patent_app_type] => utility [patent_app_number] => 12/244209 [patent_app_country] => US [patent_app_date] => 2008-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3601 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/761/07761714.pdf [firstpage_image] =>[orig_patent_app_number] => 12244209 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4528320 [patent_doc_number] => 07952382 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-31 [patent_title] => 'Impedance calibration circuit, semiconductor memory device with the impedance calibration circuit and layout method of internal resistance in the impedance calibration circuit' [patent_app_type] => utility [patent_app_number] => 12/244008 [patent_app_country] => US [patent_app_date] => 2008-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7779 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/952/07952382.pdf [firstpage_image] =>[orig_patent_app_number] => 12244008 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6361566 [patent_doc_number] => 20100079164 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-01 [patent_title] => 'Systems and Methods for Improving the PN Ratio of a Logic Gate by Adding a Non-Switching Transistor' [patent_app_type] => utility [patent_app_number] => 12/243140 [patent_app_country] => US [patent_app_date] => 2008-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3954 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20100079164.pdf [firstpage_image] =>[orig_patent_app_number] => 12243140 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4600990 [patent_doc_number] => 07977887 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-12 [patent_title] => 'Low leakage current LED drive apparatus with fault protection and diagnostics' [patent_app_type] => utility [patent_app_number] => 12/283076 [patent_app_country] => US [patent_app_date] => 2008-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2597 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/977/07977887.pdf [firstpage_image] =>[orig_patent_app_number] => 12283076 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5395531 [patent_doc_number] => 20090315594 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-24 [patent_title] => 'Source/Emitter Follower Buffer Driving a Switching Load and Having Improved Linearity' [patent_app_type] => utility [patent_app_number] => 12/199804 [patent_app_country] => US [patent_app_date] => 2008-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2922 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0315/20090315594.pdf [firstpage_image] =>[orig_patent_app_number] => 12199804 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7592697 [patent_doc_number] => 07652505 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-26 [patent_title] => 'Level conversion circuit for converting voltage amplitude of signal' [patent_app_type] => utility [patent_app_number] => 12/230007 [patent_app_country] => US [patent_app_date] => 2008-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 7909 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 357 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/652/07652505.pdf [firstpage_image] =>[orig_patent_app_number] => 12230007 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7968479 [patent_doc_number] => 07940083 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-10 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/177684 [patent_app_country] => US [patent_app_date] => 2008-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 6204 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/940/07940083.pdf [firstpage_image] =>[orig_patent_app_number] => 12177684 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4811114 [patent_doc_number] => 20080191745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-14 [patent_title] => 'HIGH-SPEED DIFFERENTIAL RECEIVER' [patent_app_type] => utility [patent_app_number] => 12/106698 [patent_app_country] => US [patent_app_date] => 2008-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2542 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0191/20080191745.pdf [firstpage_image] =>[orig_patent_app_number] => 12106698 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4504377 [patent_doc_number] => 07919980 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-05 [patent_title] => 'Configurable circuit and configuration method' [patent_app_type] => utility [patent_app_number] => 12/526344 [patent_app_country] => US [patent_app_date] => 2008-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 6992 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/919/07919980.pdf [firstpage_image] =>[orig_patent_app_number] => 12526344 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4597552 [patent_doc_number] => 07982505 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-19 [patent_title] => 'Logic circuit, address decoder circuit and semiconductor memory' [patent_app_type] => utility [patent_app_number] => 12/518793 [patent_app_country] => US [patent_app_date] => 2007-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7278 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/982/07982505.pdf [firstpage_image] =>[orig_patent_app_number] => 12518793 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4830328 [patent_doc_number] => 20080129341 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-05 [patent_title] => 'SEMICONDUCTOR APPARATUS' [patent_app_type] => utility [patent_app_number] => 11/948040 [patent_app_country] => US [patent_app_date] => 2007-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 18296 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0129/20080129341.pdf [firstpage_image] =>[orig_patent_app_number] => 11948040 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5276057 [patent_doc_number] => 20090128189 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-21 [patent_title] => 'Three dimensional programmable devices' [patent_app_type] => utility [patent_app_number] => 11/986022 [patent_app_country] => US [patent_app_date] => 2007-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 22085 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20090128189.pdf [firstpage_image] =>[orig_patent_app_number] => 11986022 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4446371 [patent_doc_number] => 07863931 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-01-04 [patent_title] => 'Flexible delay cell architecture' [patent_app_type] => utility [patent_app_number] => 11/939787 [patent_app_country] => US [patent_app_date] => 2007-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 9572 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/863/07863931.pdf [firstpage_image] =>[orig_patent_app_number] => 11939787 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4724537 [patent_doc_number] => 20080204078 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-28 [patent_title] => 'LEVEL SHIFTER FOR PREVENTING STATIC CURRENT AND PERFORMING HIGH-SPEED LEVEL SHIFTING' [patent_app_type] => utility [patent_app_number] => 11/938520 [patent_app_country] => US [patent_app_date] => 2007-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6303 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0204/20080204078.pdf [firstpage_image] =>[orig_patent_app_number] => 11938520 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4877201 [patent_doc_number] => 20080150584 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'CML CIRCUIT' [patent_app_type] => utility [patent_app_number] => 11/936276 [patent_app_country] => US [patent_app_date] => 2007-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3503 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20080150584.pdf [firstpage_image] =>[orig_patent_app_number] => 11936276 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5262773 [patent_doc_number] => 20090115458 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-07 [patent_title] => 'CMOS COMPARATOR WITH HYSTERESIS' [patent_app_type] => utility [patent_app_number] => 11/936125 [patent_app_country] => US [patent_app_date] => 2007-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4610 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20090115458.pdf [firstpage_image] =>[orig_patent_app_number] => 11936125 [rel_patent_id] =>[rel_patent_doc_number] =>)