Search

Jonathan Wade Miles

Examiner (ID: 8657, Phone: (571)270-7777 , Office: P/3731 )

Most Active Art Unit
3731
Art Unit(s)
3731, 3771, 3656
Total Applications
927
Issued Applications
727
Pending Applications
17
Abandoned Applications
193

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17961962 [patent_doc_number] => 20220342543 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => ARCHITECTURE UTILIZING A MIDDLE MAP BETWEEN LOGICAL TO PHYSICAL ADDRESS MAPPING TO SUPPORT METADATA UPDATES FOR DYNAMIC BLOCK RELOCATION [patent_app_type] => utility [patent_app_number] => 17/239025 [patent_app_country] => US [patent_app_date] => 2021-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7747 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17239025 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/239025
Architecture utilizing a middle map between logical to physical address mapping to support metadata updates for dynamic block relocation Apr 22, 2021 Issued
Array ( [id] => 18119361 [patent_doc_number] => 11550756 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => System and method for error-resilient data reduction [patent_app_type] => utility [patent_app_number] => 17/233813 [patent_app_country] => US [patent_app_date] => 2021-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 20390 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17233813 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/233813
System and method for error-resilient data reduction Apr 18, 2021 Issued
Array ( [id] => 18687142 [patent_doc_number] => 11782879 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-10 [patent_title] => System and method for secure, fast communications between processors on complex chips [patent_app_type] => utility [patent_app_number] => 17/234007 [patent_app_country] => US [patent_app_date] => 2021-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 18188 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17234007 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/234007
System and method for secure, fast communications between processors on complex chips Apr 18, 2021 Issued
Array ( [id] => 19294353 [patent_doc_number] => 12033714 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-09 [patent_title] => Interconnect architecture for three-dimensional processing systems [patent_app_type] => utility [patent_app_number] => 17/224603 [patent_app_country] => US [patent_app_date] => 2021-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6436 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17224603 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/224603
Interconnect architecture for three-dimensional processing systems Apr 6, 2021 Issued
Array ( [id] => 17899118 [patent_doc_number] => 20220308780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => ZONE BLOCK STAGING COMPONENT FOR A MEMORY SUB-SYSTEM WITH ZONED NAMESPACE [patent_app_type] => utility [patent_app_number] => 17/301213 [patent_app_country] => US [patent_app_date] => 2021-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6669 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17301213 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/301213
Zone block staging component for a memory subsystem with zoned namespace Mar 28, 2021 Issued
Array ( [id] => 17674841 [patent_doc_number] => 20220188008 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => DATA STORAGE APPARATUS AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/215276 [patent_app_country] => US [patent_app_date] => 2021-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6347 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17215276 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/215276
DATA STORAGE APPARATUS AND OPERATION METHOD THEREOF Mar 28, 2021 Abandoned
Array ( [id] => 19493058 [patent_doc_number] => 12111769 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-08 [patent_title] => Validity mapping techniques [patent_app_type] => utility [patent_app_number] => 17/630453 [patent_app_country] => US [patent_app_date] => 2021-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 13531 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17630453 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/630453
Validity mapping techniques Mar 15, 2021 Issued
Array ( [id] => 18755920 [patent_doc_number] => 20230359365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => MEMORY MANAGEMENT PROCEDURES FOR WRITE BOOST MODE [patent_app_type] => utility [patent_app_number] => 17/630113 [patent_app_country] => US [patent_app_date] => 2021-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13314 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17630113 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/630113
Memory management procedures for write boost mode Mar 15, 2021 Issued
Array ( [id] => 17009410 [patent_doc_number] => 20210240571 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-05 [patent_title] => DATA RECOVERY OPERATIONS, SUCH AS RECOVERY FROM MODIFIED NETWORK DATA MANAGEMENT PROTOCOL DATA [patent_app_type] => utility [patent_app_number] => 17/198060 [patent_app_country] => US [patent_app_date] => 2021-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16401 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17198060 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/198060
Data recovery operations, such as recovery from modified network data management protocol data Mar 9, 2021 Issued
Array ( [id] => 18414709 [patent_doc_number] => 11669250 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-06 [patent_title] => Method, device, and computer program product for managing wear level of storage system [patent_app_type] => utility [patent_app_number] => 17/193184 [patent_app_country] => US [patent_app_date] => 2021-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 12358 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17193184 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/193184
Method, device, and computer program product for managing wear level of storage system Mar 4, 2021 Issued
Array ( [id] => 18218073 [patent_doc_number] => 11593010 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-28 [patent_title] => Systems and methods for block-data clustering-based deduplication [patent_app_type] => utility [patent_app_number] => 17/187413 [patent_app_country] => US [patent_app_date] => 2021-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5208 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17187413 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/187413
Systems and methods for block-data clustering-based deduplication Feb 25, 2021 Issued
Array ( [id] => 17621771 [patent_doc_number] => 11340825 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-05-24 [patent_title] => Method, device, and computer program product for managing storage system [patent_app_type] => utility [patent_app_number] => 17/184021 [patent_app_country] => US [patent_app_date] => 2021-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7398 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17184021 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/184021
Method, device, and computer program product for managing storage system Feb 23, 2021 Issued
Array ( [id] => 18303278 [patent_doc_number] => 11625179 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-11 [patent_title] => Cache indexing using data addresses based on data fingerprints [patent_app_type] => utility [patent_app_number] => 17/180903 [patent_app_country] => US [patent_app_date] => 2021-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 10291 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17180903 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/180903
Cache indexing using data addresses based on data fingerprints Feb 21, 2021 Issued
Array ( [id] => 17682536 [patent_doc_number] => 11366790 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-21 [patent_title] => System and method for random-access manipulation of compacted data files [patent_app_type] => utility [patent_app_number] => 17/180439 [patent_app_country] => US [patent_app_date] => 2021-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 19182 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 403 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17180439 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/180439
System and method for random-access manipulation of compacted data files Feb 18, 2021 Issued
Array ( [id] => 16872277 [patent_doc_number] => 20210165744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-03 [patent_title] => REAL TIME INPUT/OUTPUT ADDRESS TRANSLATION FOR VIRTUALIZED SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/171185 [patent_app_country] => US [patent_app_date] => 2021-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5956 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17171185 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/171185
Real time input/output address translation for virtualized systems Feb 8, 2021 Issued
Array ( [id] => 18194282 [patent_doc_number] => 20230047801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => METHOD AND DEVICE FOR THE CONCEPTION OF A COMPUTATIONAL MEMORY CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/796841 [patent_app_country] => US [patent_app_date] => 2021-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12111 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17796841 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/796841
METHOD AND DEVICE FOR THE CONCEPTION OF A COMPUTATIONAL MEMORY CIRCUIT Feb 4, 2021 Pending
Array ( [id] => 17763288 [patent_doc_number] => 20220236900 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => MISALIGNED IO SEQUENCE DATA DEDUPLICATION (DEDUP) [patent_app_type] => utility [patent_app_number] => 17/160526 [patent_app_country] => US [patent_app_date] => 2021-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7545 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17160526 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/160526
Misaligned IO sequence data deduplication (dedup) Jan 27, 2021 Issued
Array ( [id] => 17054411 [patent_doc_number] => 20210263845 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-26 [patent_title] => INFORMATION PROCESSING APPARATUS TO CONTROL MEMORY ACCESS AND COMPUTER-READABLE RECORDING MEDIUM HAVING STORED THEREIN INFORMATION PROCESSING PROGRAM TO CONTROL MEMORY ACCESS [patent_app_type] => utility [patent_app_number] => 17/114553 [patent_app_country] => US [patent_app_date] => 2020-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12401 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17114553 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/114553
INFORMATION PROCESSING APPARATUS TO CONTROL MEMORY ACCESS AND COMPUTER-READABLE RECORDING MEDIUM HAVING STORED THEREIN INFORMATION PROCESSING PROGRAM TO CONTROL MEMORY ACCESS Dec 7, 2020 Abandoned
Array ( [id] => 17515663 [patent_doc_number] => 11294814 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-05 [patent_title] => Memory system having a memory controller and a memory device having a page buffer [patent_app_type] => utility [patent_app_number] => 17/107230 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 23 [patent_no_of_words] => 7465 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17107230 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/107230
Memory system having a memory controller and a memory device having a page buffer Nov 29, 2020 Issued
Array ( [id] => 17605798 [patent_doc_number] => 11334286 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-17 [patent_title] => Memory system including multiple memories connected in series [patent_app_type] => utility [patent_app_number] => 17/098757 [patent_app_country] => US [patent_app_date] => 2020-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 22 [patent_no_of_words] => 10094 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17098757 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/098757
Memory system including multiple memories connected in series Nov 15, 2020 Issued
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