Search

Jordany Nunez

Examiner (ID: 7892, Phone: (571)272-2753 , Office: P/2171 )

Most Active Art Unit
2171
Art Unit(s)
2145, 2175, 2179, 2171, 2177
Total Applications
593
Issued Applications
347
Pending Applications
31
Abandoned Applications
221

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1458726 [patent_doc_number] => 06426252 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-30 [patent_title] => 'Silicon-on-insulator vertical array DRAM cell with self-aligned buried strap' [patent_app_type] => B1 [patent_app_number] => 09/427256 [patent_app_country] => US [patent_app_date] => 1999-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 3854 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/426/06426252.pdf [firstpage_image] =>[orig_patent_app_number] => 09427256 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/427256
Silicon-on-insulator vertical array DRAM cell with self-aligned buried strap Oct 24, 1999 Issued
Array ( [id] => 4368379 [patent_doc_number] => 06287894 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Acoustic device packaged at wafer level' [patent_app_type] => 1 [patent_app_number] => 9/411316 [patent_app_country] => US [patent_app_date] => 1999-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 3804 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/287/06287894.pdf [firstpage_image] =>[orig_patent_app_number] => 411316 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/411316
Acoustic device packaged at wafer level Oct 3, 1999 Issued
Array ( [id] => 7643981 [patent_doc_number] => 06429057 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Method for manufacturing thin film transistor array panel for liquid crystal display' [patent_app_type] => B1 [patent_app_number] => 09/410760 [patent_app_country] => US [patent_app_date] => 1999-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 58 [patent_figures_cnt] => 66 [patent_no_of_words] => 15671 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/429/06429057.pdf [firstpage_image] =>[orig_patent_app_number] => 09410760 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/410760
Method for manufacturing thin film transistor array panel for liquid crystal display Sep 30, 1999 Issued
Array ( [id] => 4404363 [patent_doc_number] => 06271060 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Process of fabricating a chip scale surface mount package for semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/395095 [patent_app_country] => US [patent_app_date] => 1999-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 4983 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/271/06271060.pdf [firstpage_image] =>[orig_patent_app_number] => 395095 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/395095
Process of fabricating a chip scale surface mount package for semiconductor device Sep 12, 1999 Issued
Array ( [id] => 4394502 [patent_doc_number] => 06297087 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Process for DRAM cell production' [patent_app_type] => 1 [patent_app_number] => 9/393700 [patent_app_country] => US [patent_app_date] => 1999-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 1206 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/297/06297087.pdf [firstpage_image] =>[orig_patent_app_number] => 393700 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/393700
Process for DRAM cell production Sep 9, 1999 Issued
Array ( [id] => 4408469 [patent_doc_number] => 06309958 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/392215 [patent_app_country] => US [patent_app_date] => 1999-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 5492 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/309/06309958.pdf [firstpage_image] =>[orig_patent_app_number] => 392215 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/392215
Semiconductor device and method of manufacturing the same Sep 7, 1999 Issued
Array ( [id] => 4343747 [patent_doc_number] => 06284585 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Electronic memory device having bit lines with block selector switches' [patent_app_type] => 1 [patent_app_number] => 9/387103 [patent_app_country] => US [patent_app_date] => 1999-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5383 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/284/06284585.pdf [firstpage_image] =>[orig_patent_app_number] => 387103 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/387103
Electronic memory device having bit lines with block selector switches Aug 30, 1999 Issued
Array ( [id] => 1585404 [patent_doc_number] => 06358788 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Method of fabricating a wordline in a memory array of a semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/385396 [patent_app_country] => US [patent_app_date] => 1999-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4946 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/358/06358788.pdf [firstpage_image] =>[orig_patent_app_number] => 09385396 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/385396
Method of fabricating a wordline in a memory array of a semiconductor device Aug 29, 1999 Issued
Array ( [id] => 1549710 [patent_doc_number] => 06346454 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-12 [patent_title] => 'Method of making dual damascene interconnect structure and metal electrode capacitor' [patent_app_type] => B1 [patent_app_number] => 09/383806 [patent_app_country] => US [patent_app_date] => 1999-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3886 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/346/06346454.pdf [firstpage_image] =>[orig_patent_app_number] => 09383806 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/383806
Method of making dual damascene interconnect structure and metal electrode capacitor Aug 25, 1999 Issued
Array ( [id] => 4304184 [patent_doc_number] => 06326295 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Method and structure for improved alignment tolerance in multiple, singulated plugs and interconnection' [patent_app_type] => 1 [patent_app_number] => 9/382931 [patent_app_country] => US [patent_app_date] => 1999-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3767 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/326/06326295.pdf [firstpage_image] =>[orig_patent_app_number] => 382931 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/382931
Method and structure for improved alignment tolerance in multiple, singulated plugs and interconnection Aug 24, 1999 Issued
Array ( [id] => 4351188 [patent_doc_number] => 06291353 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Lateral patterning' [patent_app_type] => 1 [patent_app_number] => 9/377246 [patent_app_country] => US [patent_app_date] => 1999-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 32 [patent_no_of_words] => 3544 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/291/06291353.pdf [firstpage_image] =>[orig_patent_app_number] => 377246 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/377246
Lateral patterning Aug 18, 1999 Issued
Array ( [id] => 1495042 [patent_doc_number] => 06403468 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Method for forming embedded metal wiring' [patent_app_type] => B1 [patent_app_number] => 09/378010 [patent_app_country] => US [patent_app_date] => 1999-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 2765 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/403/06403468.pdf [firstpage_image] =>[orig_patent_app_number] => 09378010 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/378010
Method for forming embedded metal wiring Aug 18, 1999 Issued
Array ( [id] => 4368142 [patent_doc_number] => 06287879 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Endpoint stabilization for polishing process' [patent_app_type] => 1 [patent_app_number] => 9/371827 [patent_app_country] => US [patent_app_date] => 1999-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5112 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/287/06287879.pdf [firstpage_image] =>[orig_patent_app_number] => 371827 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/371827
Endpoint stabilization for polishing process Aug 10, 1999 Issued
Array ( [id] => 4325325 [patent_doc_number] => 06329285 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Plug fabricating method' [patent_app_type] => 1 [patent_app_number] => 9/371386 [patent_app_country] => US [patent_app_date] => 1999-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 2820 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/329/06329285.pdf [firstpage_image] =>[orig_patent_app_number] => 371386 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/371386
Plug fabricating method Aug 9, 1999 Issued
Array ( [id] => 1600446 [patent_doc_number] => 06475892 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-05 [patent_title] => 'Simplified method of patterning polysilicon gate in a semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/365407 [patent_app_country] => US [patent_app_date] => 1999-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2487 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/475/06475892.pdf [firstpage_image] =>[orig_patent_app_number] => 09365407 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/365407
Simplified method of patterning polysilicon gate in a semiconductor device Aug 1, 1999 Issued
Array ( [id] => 4326549 [patent_doc_number] => 06319768 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Method for fabricating capacitor in dram cell' [patent_app_type] => 1 [patent_app_number] => 9/357935 [patent_app_country] => US [patent_app_date] => 1999-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 2215 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/319/06319768.pdf [firstpage_image] =>[orig_patent_app_number] => 357935 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/357935
Method for fabricating capacitor in dram cell Jul 20, 1999 Issued
Array ( [id] => 4302064 [patent_doc_number] => 06251744 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Implant method to improve characteristics of high voltage isolation and high voltage breakdown' [patent_app_type] => 1 [patent_app_number] => 9/356870 [patent_app_country] => US [patent_app_date] => 1999-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 4304 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/251/06251744.pdf [firstpage_image] =>[orig_patent_app_number] => 356870 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/356870
Implant method to improve characteristics of high voltage isolation and high voltage breakdown Jul 18, 1999 Issued
Array ( [id] => 1542532 [patent_doc_number] => 06372570 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Method of formation of a capacitor on an integrated circuit' [patent_app_type] => B1 [patent_app_number] => 09/354635 [patent_app_country] => US [patent_app_date] => 1999-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 1998 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/372/06372570.pdf [firstpage_image] =>[orig_patent_app_number] => 09354635 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/354635
Method of formation of a capacitor on an integrated circuit Jul 15, 1999 Issued
Array ( [id] => 4247672 [patent_doc_number] => 06221772 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Method of cleaning the polymer from within holes on a semiconductor wafer' [patent_app_type] => 1 [patent_app_number] => 9/352747 [patent_app_country] => US [patent_app_date] => 1999-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2128 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/221/06221772.pdf [firstpage_image] =>[orig_patent_app_number] => 352747 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/352747
Method of cleaning the polymer from within holes on a semiconductor wafer Jul 13, 1999 Issued
Array ( [id] => 4381480 [patent_doc_number] => 06294447 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Method of making devices having thin dielectric layers' [patent_app_type] => 1 [patent_app_number] => 9/351971 [patent_app_country] => US [patent_app_date] => 1999-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2296 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/294/06294447.pdf [firstpage_image] =>[orig_patent_app_number] => 351971 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/351971
Method of making devices having thin dielectric layers Jul 11, 1999 Issued
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