Search

Jordany Nunez

Examiner (ID: 7892, Phone: (571)272-2753 , Office: P/2171 )

Most Active Art Unit
2171
Art Unit(s)
2145, 2175, 2179, 2171, 2177
Total Applications
593
Issued Applications
347
Pending Applications
31
Abandoned Applications
221

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4250128 [patent_doc_number] => 06207531 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Shallow trench isolation using UV/O3 passivation prior to trench fill' [patent_app_type] => 1 [patent_app_number] => 9/346977 [patent_app_country] => US [patent_app_date] => 1999-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1430 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/207/06207531.pdf [firstpage_image] =>[orig_patent_app_number] => 346977 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/346977
Shallow trench isolation using UV/O3 passivation prior to trench fill Jul 1, 1999 Issued
Array ( [id] => 4302449 [patent_doc_number] => 06251769 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Method of manufacturing contact pad' [patent_app_type] => 1 [patent_app_number] => 9/347180 [patent_app_country] => US [patent_app_date] => 1999-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2472 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/251/06251769.pdf [firstpage_image] =>[orig_patent_app_number] => 347180 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/347180
Method of manufacturing contact pad Jul 1, 1999 Issued
Array ( [id] => 4404686 [patent_doc_number] => 06271086 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Method for preventing the cluster defect of HSG' [patent_app_type] => 1 [patent_app_number] => 9/343846 [patent_app_country] => US [patent_app_date] => 1999-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 1724 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/271/06271086.pdf [firstpage_image] =>[orig_patent_app_number] => 343846 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/343846
Method for preventing the cluster defect of HSG Jun 29, 1999 Issued
Array ( [id] => 4318770 [patent_doc_number] => 06248640 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Method for forming capacitor of semiconductor device using high temperature oxidation' [patent_app_type] => 1 [patent_app_number] => 9/344585 [patent_app_country] => US [patent_app_date] => 1999-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2183 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/248/06248640.pdf [firstpage_image] =>[orig_patent_app_number] => 344585 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/344585
Method for forming capacitor of semiconductor device using high temperature oxidation Jun 24, 1999 Issued
Array ( [id] => 4336811 [patent_doc_number] => 06333260 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-25 [patent_title] => 'Semiconductor device having improved metal line structure and manufacturing method therefor' [patent_app_type] => 1 [patent_app_number] => 9/339375 [patent_app_country] => US [patent_app_date] => 1999-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 5777 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/333/06333260.pdf [firstpage_image] =>[orig_patent_app_number] => 339375 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/339375
Semiconductor device having improved metal line structure and manufacturing method therefor Jun 23, 1999 Issued
Array ( [id] => 4407097 [patent_doc_number] => 06238973 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Method for fabricating capacitors with hemispherical grains' [patent_app_type] => 1 [patent_app_number] => 9/323306 [patent_app_country] => US [patent_app_date] => 1999-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4762 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/238/06238973.pdf [firstpage_image] =>[orig_patent_app_number] => 323306 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/323306
Method for fabricating capacitors with hemispherical grains May 31, 1999 Issued
Array ( [id] => 4266894 [patent_doc_number] => 06306719 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Method for manufacturing a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/317225 [patent_app_country] => US [patent_app_date] => 1999-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 24 [patent_no_of_words] => 5047 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/306/06306719.pdf [firstpage_image] =>[orig_patent_app_number] => 317225 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/317225
Method for manufacturing a semiconductor device May 23, 1999 Issued
Array ( [id] => 1550599 [patent_doc_number] => 06399521 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Composite iridium barrier structure with oxidized refractory metal companion barrier and method for same' [patent_app_type] => B1 [patent_app_number] => 09/316646 [patent_app_country] => US [patent_app_date] => 1999-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4097 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/399/06399521.pdf [firstpage_image] =>[orig_patent_app_number] => 09316646 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/316646
Composite iridium barrier structure with oxidized refractory metal companion barrier and method for same May 20, 1999 Issued
Array ( [id] => 4271496 [patent_doc_number] => 06323115 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Method of forming semiconductor integrated circuit device with dual gate CMOS structure' [patent_app_type] => 1 [patent_app_number] => 9/314956 [patent_app_country] => US [patent_app_date] => 1999-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 28 [patent_no_of_words] => 12026 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/323/06323115.pdf [firstpage_image] =>[orig_patent_app_number] => 314956 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/314956
Method of forming semiconductor integrated circuit device with dual gate CMOS structure May 19, 1999 Issued
Array ( [id] => 1433351 [patent_doc_number] => 06340641 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-22 [patent_title] => 'Substrate flattening method and film-coated substrate made thereby' [patent_app_type] => B1 [patent_app_number] => 09/297343 [patent_app_country] => US [patent_app_date] => 1999-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 10 [patent_no_of_words] => 5649 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/340/06340641.pdf [firstpage_image] =>[orig_patent_app_number] => 09297343 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/297343
Substrate flattening method and film-coated substrate made thereby Apr 28, 1999 Issued
Array ( [id] => 4353593 [patent_doc_number] => 06218234 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Dual gate and double poly capacitor analog process integration' [patent_app_type] => 1 [patent_app_number] => 9/298934 [patent_app_country] => US [patent_app_date] => 1999-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 1631 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218234.pdf [firstpage_image] =>[orig_patent_app_number] => 298934 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/298934
Dual gate and double poly capacitor analog process integration Apr 25, 1999 Issued
Array ( [id] => 1477646 [patent_doc_number] => 06344389 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-05 [patent_title] => 'Self-aligned damascene interconnect' [patent_app_type] => B1 [patent_app_number] => 09/294076 [patent_app_country] => US [patent_app_date] => 1999-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 3254 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/344/06344389.pdf [firstpage_image] =>[orig_patent_app_number] => 09294076 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/294076
Self-aligned damascene interconnect Apr 18, 1999 Issued
Array ( [id] => 4406991 [patent_doc_number] => 06238964 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Method of fabricating a capacitor in a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/291305 [patent_app_country] => US [patent_app_date] => 1999-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3985 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/238/06238964.pdf [firstpage_image] =>[orig_patent_app_number] => 291305 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/291305
Method of fabricating a capacitor in a semiconductor device Apr 14, 1999 Issued
Array ( [id] => 4312277 [patent_doc_number] => 06242299 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Barrier layer to protect a ferroelectric capacitor after contact has been made to the capacitor electrode' [patent_app_type] => 1 [patent_app_number] => 9/283166 [patent_app_country] => US [patent_app_date] => 1999-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 3728 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/242/06242299.pdf [firstpage_image] =>[orig_patent_app_number] => 283166 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/283166
Barrier layer to protect a ferroelectric capacitor after contact has been made to the capacitor electrode Mar 31, 1999 Issued
Array ( [id] => 4289427 [patent_doc_number] => 06235571 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Uniform dielectric layer and method to form same' [patent_app_type] => 1 [patent_app_number] => 9/283116 [patent_app_country] => US [patent_app_date] => 1999-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2296 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/235/06235571.pdf [firstpage_image] =>[orig_patent_app_number] => 283116 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/283116
Uniform dielectric layer and method to form same Mar 30, 1999 Issued
Array ( [id] => 4408568 [patent_doc_number] => 06228704 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Process for manufacturing semiconductor integrated circuit device' [patent_app_type] => 1 [patent_app_number] => 9/282216 [patent_app_country] => US [patent_app_date] => 1999-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 7074 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/228/06228704.pdf [firstpage_image] =>[orig_patent_app_number] => 282216 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/282216
Process for manufacturing semiconductor integrated circuit device Mar 30, 1999 Issued
Array ( [id] => 4266860 [patent_doc_number] => 06306717 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Method of manufacturing an avalanche diode with an adjustable threshold' [patent_app_type] => 1 [patent_app_number] => 9/282025 [patent_app_country] => US [patent_app_date] => 1999-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 1813 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/306/06306717.pdf [firstpage_image] =>[orig_patent_app_number] => 282025 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/282025
Method of manufacturing an avalanche diode with an adjustable threshold Mar 29, 1999 Issued
Array ( [id] => 1553474 [patent_doc_number] => 06348375 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-19 [patent_title] => 'Method of fabricating a bit line structure for a semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/282006 [patent_app_country] => US [patent_app_date] => 1999-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 4172 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/348/06348375.pdf [firstpage_image] =>[orig_patent_app_number] => 09282006 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/282006
Method of fabricating a bit line structure for a semiconductor device Mar 28, 1999 Issued
Array ( [id] => 1594335 [patent_doc_number] => 06383861 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Method of fabricating a dual gate dielectric' [patent_app_type] => B1 [patent_app_number] => 09/252314 [patent_app_country] => US [patent_app_date] => 1999-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4193 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/383/06383861.pdf [firstpage_image] =>[orig_patent_app_number] => 09252314 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/252314
Method of fabricating a dual gate dielectric Feb 17, 1999 Issued
Array ( [id] => 1594335 [patent_doc_number] => 06383861 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Method of fabricating a dual gate dielectric' [patent_app_type] => B1 [patent_app_number] => 09/252314 [patent_app_country] => US [patent_app_date] => 1999-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4193 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/383/06383861.pdf [firstpage_image] =>[orig_patent_app_number] => 09252314 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/252314
Method of fabricating a dual gate dielectric Feb 17, 1999 Issued
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