Search

Jordany Nunez

Examiner (ID: 7892, Phone: (571)272-2753 , Office: P/2171 )

Most Active Art Unit
2171
Art Unit(s)
2145, 2175, 2179, 2171, 2177
Total Applications
593
Issued Applications
347
Pending Applications
31
Abandoned Applications
221

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6327261 [patent_doc_number] => 20020197787 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-26 [patent_title] => 'Selective polysilicon stud growth' [patent_app_type] => new [patent_app_number] => 10/209504 [patent_app_country] => US [patent_app_date] => 2002-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5527 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 28 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20020197787.pdf [firstpage_image] =>[orig_patent_app_number] => 10209504 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/209504
Selective polysilicon stud growth Jul 30, 2002 Issued
Array ( [id] => 1040510 [patent_doc_number] => 06869808 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-22 [patent_title] => 'Method for evaluating property of integrated circuitry' [patent_app_type] => utility [patent_app_number] => 10/208245 [patent_app_country] => US [patent_app_date] => 2002-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 9514 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/869/06869808.pdf [firstpage_image] =>[orig_patent_app_number] => 10208245 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/208245
Method for evaluating property of integrated circuitry Jul 30, 2002 Issued
Array ( [id] => 6765777 [patent_doc_number] => 20030100177 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-29 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => new [patent_app_number] => 10/207157 [patent_app_country] => US [patent_app_date] => 2002-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5486 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0100/20030100177.pdf [firstpage_image] =>[orig_patent_app_number] => 10207157 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/207157
Method of manufacturing semiconductor device Jul 29, 2002 Abandoned
Array ( [id] => 6686337 [patent_doc_number] => 20030030060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-13 [patent_title] => 'White semiconductor light-emitting device' [patent_app_type] => new [patent_app_number] => 10/206977 [patent_app_country] => US [patent_app_date] => 2002-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2663 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20030030060.pdf [firstpage_image] =>[orig_patent_app_number] => 10206977 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/206977
White semiconductor light-emitting device Jul 29, 2002 Abandoned
Array ( [id] => 1216574 [patent_doc_number] => 06706644 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-16 [patent_title] => 'Thermal nitrogen distribution method to improve uniformity of highly doped ultra-thin gate capacitors' [patent_app_type] => B2 [patent_app_number] => 10/206427 [patent_app_country] => US [patent_app_date] => 2002-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1958 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/706/06706644.pdf [firstpage_image] =>[orig_patent_app_number] => 10206427 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/206427
Thermal nitrogen distribution method to improve uniformity of highly doped ultra-thin gate capacitors Jul 25, 2002 Issued
Array ( [id] => 1132408 [patent_doc_number] => 06787856 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-07 [patent_title] => 'Low triggering N MOS transistor for electrostatic discharge protection device' [patent_app_type] => B2 [patent_app_number] => 10/200811 [patent_app_country] => US [patent_app_date] => 2002-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3265 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/787/06787856.pdf [firstpage_image] =>[orig_patent_app_number] => 10200811 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/200811
Low triggering N MOS transistor for electrostatic discharge protection device Jul 21, 2002 Issued
Array ( [id] => 1248263 [patent_doc_number] => 06673705 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-06 [patent_title] => 'Method of manufacturing a MISFET having post oxide films having at least two kinds of thickness' [patent_app_type] => B2 [patent_app_number] => 10/197913 [patent_app_country] => US [patent_app_date] => 2002-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 8877 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/673/06673705.pdf [firstpage_image] =>[orig_patent_app_number] => 10197913 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/197913
Method of manufacturing a MISFET having post oxide films having at least two kinds of thickness Jul 18, 2002 Issued
Array ( [id] => 6774307 [patent_doc_number] => 20030017645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-23 [patent_title] => 'Method for manufacturing circuit device' [patent_app_type] => new [patent_app_number] => 10/196087 [patent_app_country] => US [patent_app_date] => 2002-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8078 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20030017645.pdf [firstpage_image] =>[orig_patent_app_number] => 10196087 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/196087
Method for manufacturing circuit device Jul 15, 2002 Issued
Array ( [id] => 779208 [patent_doc_number] => 06995075 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-02-07 [patent_title] => 'Process for forming a fragile layer inside of a single crystalline substrate' [patent_app_type] => utility [patent_app_number] => 10/195045 [patent_app_country] => US [patent_app_date] => 2002-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7455 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/995/06995075.pdf [firstpage_image] =>[orig_patent_app_number] => 10195045 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/195045
Process for forming a fragile layer inside of a single crystalline substrate Jul 11, 2002 Issued
Array ( [id] => 1223723 [patent_doc_number] => 06699761 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-02 [patent_title] => 'Method for fabricating y-direction, self-alignment mask ROM device' [patent_app_type] => B2 [patent_app_number] => 10/064396 [patent_app_country] => US [patent_app_date] => 2002-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 2795 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/699/06699761.pdf [firstpage_image] =>[orig_patent_app_number] => 10064396 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/064396
Method for fabricating y-direction, self-alignment mask ROM device Jul 9, 2002 Issued
Array ( [id] => 1305942 [patent_doc_number] => 06621117 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-16 [patent_title] => 'Semiconductor device having memory cell and peripheral circuitry with dummy electrode' [patent_app_type] => B2 [patent_app_number] => 10/191458 [patent_app_country] => US [patent_app_date] => 2002-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 4319 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/621/06621117.pdf [firstpage_image] =>[orig_patent_app_number] => 10191458 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/191458
Semiconductor device having memory cell and peripheral circuitry with dummy electrode Jul 9, 2002 Issued
Array ( [id] => 6837209 [patent_doc_number] => 20030034549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-20 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => new [patent_app_number] => 10/190547 [patent_app_country] => US [patent_app_date] => 2002-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5084 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20030034549.pdf [firstpage_image] =>[orig_patent_app_number] => 10190547 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/190547
Semiconductor integrated circuit device having a test path Jul 8, 2002 Issued
Array ( [id] => 6044319 [patent_doc_number] => 20020167036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-14 [patent_title] => 'Method for fabricating DRAM cell and DRAM cell fabricated thereby' [patent_app_type] => new [patent_app_number] => 10/189737 [patent_app_country] => US [patent_app_date] => 2002-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6556 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0167/20020167036.pdf [firstpage_image] =>[orig_patent_app_number] => 10189737 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/189737
DRAM cell having electrode with protection layer Jul 7, 2002 Issued
Array ( [id] => 1225220 [patent_doc_number] => 06700205 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-02 [patent_title] => 'Semiconductor devices having contact plugs and local interconnects' [patent_app_type] => B2 [patent_app_number] => 10/191695 [patent_app_country] => US [patent_app_date] => 2002-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 20 [patent_no_of_words] => 4692 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/700/06700205.pdf [firstpage_image] =>[orig_patent_app_number] => 10191695 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/191695
Semiconductor devices having contact plugs and local interconnects Jul 7, 2002 Issued
Array ( [id] => 6841098 [patent_doc_number] => 20030146445 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-07 [patent_title] => 'Electrode structure of LED and manufacturing of the same' [patent_app_type] => new [patent_app_number] => 10/189847 [patent_app_country] => US [patent_app_date] => 2002-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3484 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20030146445.pdf [firstpage_image] =>[orig_patent_app_number] => 10189847 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/189847
Electrode structure of LED and manufacturing of the same Jul 4, 2002 Abandoned
Array ( [id] => 6107146 [patent_doc_number] => 20020171099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-21 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => new [patent_app_number] => 10/188868 [patent_app_country] => US [patent_app_date] => 2002-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4162 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0171/20020171099.pdf [firstpage_image] =>[orig_patent_app_number] => 10188868 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/188868
Semiconductor device and manufacturing method thereof Jul 4, 2002 Abandoned
Array ( [id] => 1179879 [patent_doc_number] => 06740550 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-25 [patent_title] => 'Methods of manufacturing semiconductor devices having chamfered silicide layers therein' [patent_app_type] => B2 [patent_app_number] => 10/190086 [patent_app_country] => US [patent_app_date] => 2002-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 40 [patent_no_of_words] => 11712 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/740/06740550.pdf [firstpage_image] =>[orig_patent_app_number] => 10190086 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/190086
Methods of manufacturing semiconductor devices having chamfered silicide layers therein Jul 2, 2002 Issued
Array ( [id] => 961054 [patent_doc_number] => 06951767 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-10-04 [patent_title] => 'Development hastened stability of titanium nitride for APM etching rate monitor' [patent_app_type] => utility [patent_app_number] => 10/187705 [patent_app_country] => US [patent_app_date] => 2002-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 1485 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/951/06951767.pdf [firstpage_image] =>[orig_patent_app_number] => 10187705 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/187705
Development hastened stability of titanium nitride for APM etching rate monitor Jul 1, 2002 Issued
Array ( [id] => 1223737 [patent_doc_number] => 06699766 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-02 [patent_title] => 'Method of fabricating an integral capacitor and gate transistor having nitride and oxide polish stop layers using chemical mechanical polishing elimination' [patent_app_type] => B1 [patent_app_number] => 10/185537 [patent_app_country] => US [patent_app_date] => 2002-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 7721 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/699/06699766.pdf [firstpage_image] =>[orig_patent_app_number] => 10185537 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/185537
Method of fabricating an integral capacitor and gate transistor having nitride and oxide polish stop layers using chemical mechanical polishing elimination Jun 30, 2002 Issued
Array ( [id] => 7433423 [patent_doc_number] => 20040002183 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-01 [patent_title] => 'CVD deposition of M-ON gate dielectrics' [patent_app_type] => new [patent_app_number] => 10/185965 [patent_app_country] => US [patent_app_date] => 2002-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1626 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20040002183.pdf [firstpage_image] =>[orig_patent_app_number] => 10185965 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/185965
CVD deposition of M-ON gate dielectrics Jun 27, 2002 Abandoned
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