Search

Jorge L. Salazar Jr.

Examiner (ID: 2284, Phone: (571)272-9326 , Office: P/2842 )

Most Active Art Unit
2843
Art Unit(s)
2843, 2842
Total Applications
1048
Issued Applications
900
Pending Applications
124
Abandoned Applications
52

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12966931 [patent_doc_number] => 09875205 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-01-23 [patent_title] => Network of memory systems [patent_app_type] => utility [patent_app_number] => 14/217161 [patent_app_country] => US [patent_app_date] => 2014-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10213 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14217161 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/217161
Network of memory systems Mar 16, 2014 Issued
Array ( [id] => 9599032 [patent_doc_number] => 20140195713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-10 [patent_title] => 'Computer System Including CPU or Peripheral Bridge to Communicate Serial Bits of Peripheral Component Interconnect Bus Transaction and Low Voltage Differential Signal Channel to Convey the Serial Bits' [patent_app_type] => utility [patent_app_number] => 14/209922 [patent_app_country] => US [patent_app_date] => 2014-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 23865 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14209922 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/209922
Computer system including CPU or peripheral bridge directly connected to a low voltage differential signal channel that communicates serial bits of a peripheral component interconnect bus transaction in opposite directions Mar 12, 2014 Issued
Array ( [id] => 10059280 [patent_doc_number] => 09098642 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-04 [patent_title] => 'Dual bus standard switching bus controller' [patent_app_type] => utility [patent_app_number] => 14/194893 [patent_app_country] => US [patent_app_date] => 2014-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3275 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14194893 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/194893
Dual bus standard switching bus controller Mar 2, 2014 Issued
Array ( [id] => 11889946 [patent_doc_number] => 09760507 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-12 [patent_title] => 'Data processing device and data processing method' [patent_app_type] => utility [patent_app_number] => 14/176606 [patent_app_country] => US [patent_app_date] => 2014-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6226 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14176606 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/176606
Data processing device and data processing method Feb 9, 2014 Issued
Array ( [id] => 12039235 [patent_doc_number] => 09817468 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-14 [patent_title] => 'System and method for automatic detection and switching between USB host and device rolls on a type-A connector' [patent_app_type] => utility [patent_app_number] => 14/171340 [patent_app_country] => US [patent_app_date] => 2014-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6217 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14171340 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/171340
System and method for automatic detection and switching between USB host and device rolls on a type-A connector Feb 2, 2014 Issued
Array ( [id] => 9974134 [patent_doc_number] => 09021171 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-04-28 [patent_title] => 'Bus system including a master device, a slave device, an interconnector coupled between the master device and the slave device, and an operating method thereof' [patent_app_type] => utility [patent_app_number] => 14/170086 [patent_app_country] => US [patent_app_date] => 2014-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7685 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14170086 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/170086
Bus system including a master device, a slave device, an interconnector coupled between the master device and the slave device, and an operating method thereof Jan 30, 2014 Issued
Array ( [id] => 9479280 [patent_doc_number] => 20140136743 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-15 [patent_title] => 'DATA PROCESSING DEVICE AND DATA PROCESSING METHOD' [patent_app_type] => utility [patent_app_number] => 14/158619 [patent_app_country] => US [patent_app_date] => 2014-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9753 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14158619 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/158619
Data processing device and data processing method Jan 16, 2014 Issued
Array ( [id] => 10302399 [patent_doc_number] => 20150187399 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-02 [patent_title] => 'PULSE MECHANISM FOR MEMORY CIRCUIT INTERRUPTION' [patent_app_type] => utility [patent_app_number] => 14/145116 [patent_app_country] => US [patent_app_date] => 2013-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2811 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14145116 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/145116
Pulse mechanism for memory circuit interruption Dec 30, 2013 Issued
Array ( [id] => 9592752 [patent_doc_number] => 08782317 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-07-15 [patent_title] => 'Computer system, method for accessing peripheral component interconnect express endpoint device, and apparatus' [patent_app_type] => utility [patent_app_number] => 14/143460 [patent_app_country] => US [patent_app_date] => 2013-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 10984 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14143460 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/143460
Computer system, method for accessing peripheral component interconnect express endpoint device, and apparatus Dec 29, 2013 Issued
Array ( [id] => 11823786 [patent_doc_number] => 20170212724 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-27 [patent_title] => 'SCALABLE INPUT/OUTPUT SYSTEM AND TECHNIQUES' [patent_app_type] => utility [patent_app_number] => 15/039934 [patent_app_country] => US [patent_app_date] => 2013-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9416 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15039934 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/039934
Scalable input/output system and techniques to transmit data between domains without a central processor Dec 26, 2013 Issued
Array ( [id] => 10502106 [patent_doc_number] => 09230507 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-05 [patent_title] => 'System and method for transitioning an electronic device from a first power mode to a second power mode' [patent_app_type] => utility [patent_app_number] => 14/135005 [patent_app_country] => US [patent_app_date] => 2013-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5793 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14135005 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/135005
System and method for transitioning an electronic device from a first power mode to a second power mode Dec 18, 2013 Issued
Array ( [id] => 10059281 [patent_doc_number] => 09098643 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-04 [patent_title] => 'Multiple serial port controller' [patent_app_type] => utility [patent_app_number] => 14/134166 [patent_app_country] => US [patent_app_date] => 2013-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 1782 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14134166 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/134166
Multiple serial port controller Dec 18, 2013 Issued
Array ( [id] => 10269141 [patent_doc_number] => 20150154138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-04 [patent_title] => 'WIDE PORT EMULATION AT SERIAL ATTACHED SCSI EXPANDERS' [patent_app_type] => utility [patent_app_number] => 14/096204 [patent_app_country] => US [patent_app_date] => 2013-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3245 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14096204 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/096204
Wide port emulation at serial attached SCSI expanders using virtual physical links Dec 3, 2013 Issued
Array ( [id] => 11801466 [patent_doc_number] => 09542343 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-10 [patent_title] => 'Memory modules with reduced rank loading and memory systems including same' [patent_app_type] => utility [patent_app_number] => 14/091385 [patent_app_country] => US [patent_app_date] => 2013-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 10616 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14091385 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/091385
Memory modules with reduced rank loading and memory systems including same Nov 26, 2013 Issued
Array ( [id] => 9571470 [patent_doc_number] => 20140189183 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'MEMORY SYSTEM AND DRIVING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/090521 [patent_app_country] => US [patent_app_date] => 2013-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7120 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14090521 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/090521
Memory system having first and second memory devices and driving method thereof Nov 25, 2013 Issued
Array ( [id] => 10264677 [patent_doc_number] => 20150149674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-28 [patent_title] => 'EMBEDDED STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 14/090149 [patent_app_country] => US [patent_app_date] => 2013-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2919 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14090149 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/090149
Embedded storage device including a plurality of storage units coupled via relay bus Nov 25, 2013 Issued
Array ( [id] => 10264676 [patent_doc_number] => 20150149673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-28 [patent_title] => 'FENCE MANAGEMENT OVER MULTIPLE BUSSES' [patent_app_type] => utility [patent_app_number] => 14/089237 [patent_app_country] => US [patent_app_date] => 2013-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5435 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14089237 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/089237
Synchronizing transactions for a single master over multiple busses Nov 24, 2013 Issued
Array ( [id] => 10907430 [patent_doc_number] => 20140310444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-16 [patent_title] => 'DYNAMIC BALANCING OF BUS BANDWIDTH ACROSS MULTIPLE ROUTES' [patent_app_type] => utility [patent_app_number] => 14/089314 [patent_app_country] => US [patent_app_date] => 2013-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3919 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14089314 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/089314
Method and system for using feedback information for selecting a routing bus for a memory transaction Nov 24, 2013 Issued
Array ( [id] => 11523548 [patent_doc_number] => 09606948 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-28 [patent_title] => 'CAN bus edge timing control for dominant-to-recessive transitions' [patent_app_type] => utility [patent_app_number] => 14/087879 [patent_app_country] => US [patent_app_date] => 2013-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 6207 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14087879 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/087879
CAN bus edge timing control for dominant-to-recessive transitions Nov 21, 2013 Issued
Array ( [id] => 11213840 [patent_doc_number] => 09442875 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-13 [patent_title] => 'Multi-protocol combined receiver for receiving and processing data of multiple protocols' [patent_app_type] => utility [patent_app_number] => 14/084507 [patent_app_country] => US [patent_app_date] => 2013-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3365 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14084507 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/084507
Multi-protocol combined receiver for receiving and processing data of multiple protocols Nov 18, 2013 Issued
Menu