Search

Jorge L. Salazar Jr.

Examiner (ID: 2284, Phone: (571)272-9326 , Office: P/2842 )

Most Active Art Unit
2843
Art Unit(s)
2843, 2842
Total Applications
1048
Issued Applications
900
Pending Applications
124
Abandoned Applications
52

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9235874 [patent_doc_number] => 08601190 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-03 [patent_title] => 'Providing multiple communication protocols for a control system having a master controller and a slave controller' [patent_app_type] => utility [patent_app_number] => 13/167922 [patent_app_country] => US [patent_app_date] => 2011-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7939 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13167922 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/167922
Providing multiple communication protocols for a control system having a master controller and a slave controller Jun 23, 2011 Issued
Array ( [id] => 8060431 [patent_doc_number] => 20110246806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-06 [patent_title] => 'BLOCK BASED POWER MANAGEMENT' [patent_app_type] => utility [patent_app_number] => 13/160234 [patent_app_country] => US [patent_app_date] => 2011-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5939 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20110246806.pdf [firstpage_image] =>[orig_patent_app_number] => 13160234 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/160234
Hardware-based power management of functional blocks Jun 13, 2011 Issued
Array ( [id] => 8524728 [patent_doc_number] => 20120324136 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-20 [patent_title] => 'REPRESENTATION OF DATA RELATIVE TO VARYING THRESHOLDS' [patent_app_type] => utility [patent_app_number] => 13/159670 [patent_app_country] => US [patent_app_date] => 2011-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4881 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13159670 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/159670
Representation of data relative to varying thresholds Jun 13, 2011 Issued
Array ( [id] => 8511804 [patent_doc_number] => 20120311212 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-06 [patent_title] => 'AVOIDING NON-POSTED REQUEST DEADLOCKS IN DEVICES' [patent_app_type] => utility [patent_app_number] => 13/151073 [patent_app_country] => US [patent_app_date] => 2011-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5961 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13151073 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/151073
Avoiding non-posted request deadlocks in devices by holding the sending of requests May 31, 2011 Issued
Array ( [id] => 7569181 [patent_doc_number] => 20110289244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-24 [patent_title] => 'TELEVISION WITH INTEGRATED ASYNCHRONOUS/SYNCHRONOUS KVMP SIGNAL SWITCH FOR CONSOLE AND PERIPHERAL DEVICES' [patent_app_type] => utility [patent_app_number] => 13/151104 [patent_app_country] => US [patent_app_date] => 2011-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6189 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0289/20110289244.pdf [firstpage_image] =>[orig_patent_app_number] => 13151104 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/151104
TELEVISION WITH INTEGRATED ASYNCHRONOUS/SYNCHRONOUS KVMP SIGNAL SWITCH FOR CONSOLE AND PERIPHERAL DEVICES May 31, 2011 Abandoned
Array ( [id] => 8511803 [patent_doc_number] => 20120311210 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-06 [patent_title] => 'SYSTEM AND METHOD FOR OPTIMIZING SLAVE TRANSACTION ID WIDTH BASED ON SPARSE CONNECTION IN MULTILAYER MULTILEVEL INTERCONNECT SYSTEM-ON-CHIP ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 13/118603 [patent_app_country] => US [patent_app_date] => 2011-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7360 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13118603 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/118603
System and method for optimizing slave transaction ID width based on sparse connection in multilayer multilevel interconnect system-on-chip architecture May 30, 2011 Issued
Array ( [id] => 8511800 [patent_doc_number] => 20120311208 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-06 [patent_title] => 'METHOD AND SYSTEM FOR PROCESSING COMMANDS ON AN INFINIBAND HOST CHANNEL ADAPTOR' [patent_app_type] => utility [patent_app_number] => 13/149436 [patent_app_country] => US [patent_app_date] => 2011-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12545 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13149436 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/149436
Method and system for receiving commands using a scoreboard on an infiniband host channel adaptor May 30, 2011 Issued
Array ( [id] => 9289246 [patent_doc_number] => 08645601 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-04 [patent_title] => 'Methods and systems for performing serial data communication between a host device and a connected device' [patent_app_type] => utility [patent_app_number] => 13/149103 [patent_app_country] => US [patent_app_date] => 2011-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5804 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13149103 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/149103
Methods and systems for performing serial data communication between a host device and a connected device May 30, 2011 Issued
Array ( [id] => 9102596 [patent_doc_number] => 08566490 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-22 [patent_title] => 'Method and system for address allocation for a plurality of devices connected to a multi-master bus' [patent_app_type] => utility [patent_app_number] => 13/118571 [patent_app_country] => US [patent_app_date] => 2011-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2775 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13118571 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/118571
Method and system for address allocation for a plurality of devices connected to a multi-master bus May 29, 2011 Issued
Array ( [id] => 8511801 [patent_doc_number] => 20120311209 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-06 [patent_title] => 'SYSTEM, CIRCUIT AND METHOD FOR IMPROVING SYSTEM-ON-CHIP BANDWIDTH PERFORMANCE FOR HIGH LATENCY PERIPHERAL READ ACCESSES' [patent_app_type] => utility [patent_app_number] => 13/118493 [patent_app_country] => US [patent_app_date] => 2011-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6845 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13118493 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/118493
System, circuit and method for improving system-on-chip bandwidth performance for high latency peripheral read accesses May 29, 2011 Issued
Array ( [id] => 8504440 [patent_doc_number] => 20120303848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-29 [patent_title] => 'SYSTEM AND METHOD FOR ALLOCATING TRANSACTION ID IN A SYSTEM WITH A PLURALITY OF PROCESSING MODULES' [patent_app_type] => utility [patent_app_number] => 13/118376 [patent_app_country] => US [patent_app_date] => 2011-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5779 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13118376 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/118376
System and method for allocating transaction ID in a system with a plurality of processing modules May 27, 2011 Issued
Array ( [id] => 9116114 [patent_doc_number] => 08572306 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-29 [patent_title] => 'USB transaction translator and USB transaction translation method' [patent_app_type] => utility [patent_app_number] => 13/089834 [patent_app_country] => US [patent_app_date] => 2011-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3257 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13089834 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/089834
USB transaction translator and USB transaction translation method Apr 18, 2011 Issued
Array ( [id] => 8319643 [patent_doc_number] => 08234436 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-31 [patent_title] => 'Computer system including peripheral bridge to communicate serial bits of peripheral component interconnect bus transaction and low voltage differential signal channel to convey the serial bits' [patent_app_type] => utility [patent_app_number] => 13/087912 [patent_app_country] => US [patent_app_date] => 2011-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 22460 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13087912 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/087912
Computer system including peripheral bridge to communicate serial bits of peripheral component interconnect bus transaction and low voltage differential signal channel to convey the serial bits Apr 14, 2011 Issued
Array ( [id] => 6181652 [patent_doc_number] => 20110179209 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-21 [patent_title] => 'Terminal Apparatus and Method for Controlling Processing of an Interrupt Event' [patent_app_type] => utility [patent_app_number] => 13/073608 [patent_app_country] => US [patent_app_date] => 2011-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6502 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20110179209.pdf [firstpage_image] =>[orig_patent_app_number] => 13073608 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/073608
Terminal apparatus and method for controlling processing of an interrupt event Mar 27, 2011 Issued
Array ( [id] => 11220617 [patent_doc_number] => 09448954 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-20 [patent_title] => 'Method and an apparatus for coherency control' [patent_app_type] => utility [patent_app_number] => 14/000216 [patent_app_country] => US [patent_app_date] => 2011-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6912 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14000216 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/000216
Method and an apparatus for coherency control Feb 27, 2011 Issued
Array ( [id] => 8998032 [patent_doc_number] => 08521937 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-27 [patent_title] => 'Method and apparatus for interfacing multiple dies with mapping to modify source identity' [patent_app_type] => utility [patent_app_number] => 13/028383 [patent_app_country] => US [patent_app_date] => 2011-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 7050 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13028383 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/028383
Method and apparatus for interfacing multiple dies with mapping to modify source identity Feb 15, 2011 Issued
Array ( [id] => 8349111 [patent_doc_number] => 20120210040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-16 [patent_title] => 'MICRO-CROSSBAR AND ON-DIE DATA NETWORK' [patent_app_type] => utility [patent_app_number] => 13/026582 [patent_app_country] => US [patent_app_date] => 2011-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5479 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13026582 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/026582
Micro crossbar switch and on-die data network using the same Feb 13, 2011 Issued
Array ( [id] => 9089302 [patent_doc_number] => 08560749 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-15 [patent_title] => 'Techniques for managing power consumption state of a processor involving use of latency tolerance report value' [patent_app_type] => utility [patent_app_number] => 13/025492 [patent_app_country] => US [patent_app_date] => 2011-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3879 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13025492 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/025492
Techniques for managing power consumption state of a processor involving use of latency tolerance report value Feb 10, 2011 Issued
Array ( [id] => 6067399 [patent_doc_number] => 20110202703 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-18 [patent_title] => 'RELIABILITY OF A COMPUTER SYSTEM EMPLOYING PCI EXPRESS DEVICES' [patent_app_type] => utility [patent_app_number] => 13/024456 [patent_app_country] => US [patent_app_date] => 2011-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9103 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0202/20110202703.pdf [firstpage_image] =>[orig_patent_app_number] => 13024456 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/024456
PCI express multiplier device Feb 9, 2011 Issued
Array ( [id] => 10137647 [patent_doc_number] => 09170967 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-27 [patent_title] => 'System and method for transmitting information from a transmitter to a receiver via a single line' [patent_app_type] => utility [patent_app_number] => 13/577569 [patent_app_country] => US [patent_app_date] => 2011-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2279 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13577569 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/577569
System and method for transmitting information from a transmitter to a receiver via a single line Feb 7, 2011 Issued
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