Search

Jose L Couso

Examiner (ID: 6293, Phone: (571)272-7388 , Office: P/2667 )

Most Active Art Unit
2667
Art Unit(s)
2606, 2714, 2667, 2616, 2721, 2624, 2621
Total Applications
2714
Issued Applications
2159
Pending Applications
113
Abandoned Applications
442

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4222091 [patent_doc_number] => 06010934 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-04 [patent_title] => 'Method of making nanometer Si islands for single electron transistors' [patent_app_type] => 1 [patent_app_number] => 9/033527 [patent_app_country] => US [patent_app_date] => 1998-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 2316 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/010/06010934.pdf [firstpage_image] =>[orig_patent_app_number] => 033527 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/033527
Method of making nanometer Si islands for single electron transistors Mar 1, 1998 Issued
Array ( [id] => 4232317 [patent_doc_number] => 06117696 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Circuit and method for measuring and forcing an internal voltage of an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/031934 [patent_app_country] => US [patent_app_date] => 1998-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 19 [patent_no_of_words] => 3138 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/117/06117696.pdf [firstpage_image] =>[orig_patent_app_number] => 031934 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/031934
Circuit and method for measuring and forcing an internal voltage of an integrated circuit Feb 26, 1998 Issued
Array ( [id] => 4097426 [patent_doc_number] => 06048742 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'Process for measuring the thickness and composition of thin semiconductor films deposited on semiconductor wafers' [patent_app_type] => 1 [patent_app_number] => 9/035573 [patent_app_country] => US [patent_app_date] => 1998-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7033 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/048/06048742.pdf [firstpage_image] =>[orig_patent_app_number] => 035573 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/035573
Process for measuring the thickness and composition of thin semiconductor films deposited on semiconductor wafers Feb 25, 1998 Issued
Array ( [id] => 4029306 [patent_doc_number] => 05994176 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Method for forming self-aligned silicided MOS transistors with asymmetric ESD protecting transistors' [patent_app_type] => 1 [patent_app_number] => 9/025971 [patent_app_country] => US [patent_app_date] => 1998-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4186 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/994/05994176.pdf [firstpage_image] =>[orig_patent_app_number] => 025971 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/025971
Method for forming self-aligned silicided MOS transistors with asymmetric ESD protecting transistors Feb 18, 1998 Issued
Array ( [id] => 4218573 [patent_doc_number] => 06040198 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'Element concentration measuring method and apparatus, and semiconductor device fabrication method and apparatus' [patent_app_type] => 1 [patent_app_number] => 9/018852 [patent_app_country] => US [patent_app_date] => 1998-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 7444 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/040/06040198.pdf [firstpage_image] =>[orig_patent_app_number] => 018852 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/018852
Element concentration measuring method and apparatus, and semiconductor device fabrication method and apparatus Feb 3, 1998 Issued
Array ( [id] => 4181290 [patent_doc_number] => 06020239 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'Pillar transistor incorporating a body contact' [patent_app_type] => 1 [patent_app_number] => 9/014960 [patent_app_country] => US [patent_app_date] => 1998-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 44 [patent_no_of_words] => 5936 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/020/06020239.pdf [firstpage_image] =>[orig_patent_app_number] => 014960 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/014960
Pillar transistor incorporating a body contact Jan 27, 1998 Issued
Array ( [id] => 4215591 [patent_doc_number] => 06087246 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Method for fabricating dual gate semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/012243 [patent_app_country] => US [patent_app_date] => 1998-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 1907 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/087/06087246.pdf [firstpage_image] =>[orig_patent_app_number] => 012243 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/012243
Method for fabricating dual gate semiconductor device Jan 22, 1998 Issued
Array ( [id] => 4130134 [patent_doc_number] => 06033960 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Method to improve the breakdown voltage of P-channel devices' [patent_app_type] => 1 [patent_app_number] => 9/006600 [patent_app_country] => US [patent_app_date] => 1998-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 1666 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/033/06033960.pdf [firstpage_image] =>[orig_patent_app_number] => 006600 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/006600
Method to improve the breakdown voltage of P-channel devices Jan 12, 1998 Issued
Array ( [id] => 4233446 [patent_doc_number] => 06074890 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Method of fabricating suspended single crystal silicon micro electro mechanical system (MEMS) devices' [patent_app_type] => 1 [patent_app_number] => 9/004683 [patent_app_country] => US [patent_app_date] => 1998-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 30 [patent_no_of_words] => 3884 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/074/06074890.pdf [firstpage_image] =>[orig_patent_app_number] => 004683 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/004683
Method of fabricating suspended single crystal silicon micro electro mechanical system (MEMS) devices Jan 7, 1998 Issued
Array ( [id] => 3934874 [patent_doc_number] => 05972749 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Method for preventing P1 punchthrough' [patent_app_type] => 1 [patent_app_number] => 9/002783 [patent_app_country] => US [patent_app_date] => 1998-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3347 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/972/05972749.pdf [firstpage_image] =>[orig_patent_app_number] => 002783 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/002783
Method for preventing P1 punchthrough Jan 4, 1998 Issued
Array ( [id] => 3936803 [patent_doc_number] => 05915171 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-22 [patent_title] => 'Process of fabricating an antifuse structure' [patent_app_type] => 1 [patent_app_number] => 9/000962 [patent_app_country] => US [patent_app_date] => 1997-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1967 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/915/05915171.pdf [firstpage_image] =>[orig_patent_app_number] => 000962 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/000962
Process of fabricating an antifuse structure Dec 29, 1997 Issued
Array ( [id] => 4102686 [patent_doc_number] => 06051487 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Semiconductor device fabrication using a sacrificial plug for defining a region for a gate electrode' [patent_app_type] => 1 [patent_app_number] => 8/993612 [patent_app_country] => US [patent_app_date] => 1997-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 15 [patent_no_of_words] => 4369 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/051/06051487.pdf [firstpage_image] =>[orig_patent_app_number] => 993612 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/993612
Semiconductor device fabrication using a sacrificial plug for defining a region for a gate electrode Dec 17, 1997 Issued
Array ( [id] => 4215471 [patent_doc_number] => 06087238 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Semiconductor device having reduced-width polysilicon gate and non-oxidizing barrier layer and method of manufacture thereof' [patent_app_type] => 1 [patent_app_number] => 8/992383 [patent_app_country] => US [patent_app_date] => 1997-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3226 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/087/06087238.pdf [firstpage_image] =>[orig_patent_app_number] => 992383 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/992383
Semiconductor device having reduced-width polysilicon gate and non-oxidizing barrier layer and method of manufacture thereof Dec 16, 1997 Issued
Array ( [id] => 4172434 [patent_doc_number] => 06083791 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Self-aligned stacked gate etch process for fabricating a two-transistor EEPROM cell' [patent_app_type] => 1 [patent_app_number] => 8/990493 [patent_app_country] => US [patent_app_date] => 1997-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 29 [patent_no_of_words] => 4041 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/083/06083791.pdf [firstpage_image] =>[orig_patent_app_number] => 990493 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/990493
Self-aligned stacked gate etch process for fabricating a two-transistor EEPROM cell Dec 14, 1997 Issued
Array ( [id] => 3967378 [patent_doc_number] => 05956614 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Process for forming a metal-silicide gate for dynamic random access memory' [patent_app_type] => 1 [patent_app_number] => 8/989983 [patent_app_country] => US [patent_app_date] => 1997-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 2011 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/956/05956614.pdf [firstpage_image] =>[orig_patent_app_number] => 989983 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/989983
Process for forming a metal-silicide gate for dynamic random access memory Dec 11, 1997 Issued
Array ( [id] => 4153854 [patent_doc_number] => 06103553 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Method of manufacturing a known good die utilizing a substrate' [patent_app_type] => 1 [patent_app_number] => 8/986851 [patent_app_country] => US [patent_app_date] => 1997-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3160 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/103/06103553.pdf [firstpage_image] =>[orig_patent_app_number] => 986851 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/986851
Method of manufacturing a known good die utilizing a substrate Dec 7, 1997 Issued
Array ( [id] => 3952906 [patent_doc_number] => 05940705 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Methods of forming floating-gate FFRAM devices' [patent_app_type] => 1 [patent_app_number] => 8/974084 [patent_app_country] => US [patent_app_date] => 1997-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 4522 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/940/05940705.pdf [firstpage_image] =>[orig_patent_app_number] => 974084 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/974084
Methods of forming floating-gate FFRAM devices Nov 18, 1997 Issued
Array ( [id] => 4003110 [patent_doc_number] => 06004872 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-21 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/959845 [patent_app_country] => US [patent_app_date] => 1997-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 4944 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/004/06004872.pdf [firstpage_image] =>[orig_patent_app_number] => 959845 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/959845
Method of manufacturing semiconductor device Oct 28, 1997 Issued
Array ( [id] => 4197479 [patent_doc_number] => 06013548 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-11 [patent_title] => 'Self-aligned diffused source vertical transistors with deep trench capacitors in a 4F-square memory cell array' [patent_app_type] => 1 [patent_app_number] => 8/959893 [patent_app_country] => US [patent_app_date] => 1997-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 72 [patent_no_of_words] => 20156 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/013/06013548.pdf [firstpage_image] =>[orig_patent_app_number] => 959893 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/959893
Self-aligned diffused source vertical transistors with deep trench capacitors in a 4F-square memory cell array Oct 28, 1997 Issued
Array ( [id] => 3975852 [patent_doc_number] => 05937269 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Graphics assisted manufacturing process for thin-film devices' [patent_app_type] => 1 [patent_app_number] => 8/960695 [patent_app_country] => US [patent_app_date] => 1997-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 4402 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/937/05937269.pdf [firstpage_image] =>[orig_patent_app_number] => 960695 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/960695
Graphics assisted manufacturing process for thin-film devices Oct 28, 1997 Issued
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