![](/images/general/no_picture/200_user.png)
Jose L Couso
Examiner (ID: 6293, Phone: (571)272-7388 , Office: P/2667 )
Most Active Art Unit | 2667 |
Art Unit(s) | 2606, 2714, 2667, 2616, 2721, 2624, 2621 |
Total Applications | 2714 |
Issued Applications | 2159 |
Pending Applications | 113 |
Abandoned Applications | 442 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 3934477
[patent_doc_number] => 05972723
[patent_country] => US
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[patent_issue_date] => 1999-10-26
[patent_title] => 'Enhanced thin film wiring net repair process'
[patent_app_type] => 1
[patent_app_number] => 8/955204
[patent_app_country] => US
[patent_app_date] => 1997-10-21
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/955204 | Enhanced thin film wiring net repair process | Oct 20, 1997 | Issued |
Array
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[patent_issue_date] => 2000-02-15
[patent_title] => 'Methods of forming field effect transistors having graded drain region doping profiles therein'
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Array
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[patent_issue_date] => 2000-05-02
[patent_title] => 'Methods for determining on-chip interconnect process parameters'
[patent_app_type] => 1
[patent_app_number] => 8/937393
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[patent_app_date] => 1997-09-25
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Array
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[patent_issue_date] => 1999-08-24
[patent_title] => 'Fabrication of a gate electrode stack using a patterned oxide layer'
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Array
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Array
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Array
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Array
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Array
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[id] => 4070837
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Array
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Array
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Array
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[id] => 4085470
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[patent_title] => 'Method of forming a Ta.sub.2 O.sub.5 dielectric layer with amorphous diffusion barrier layer and method of forming a capacitor having a b. Ta.su2 O.sub.5 dielectric layer with amorphous diffusion barrier layer'
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Array
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[id] => 4191086
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[patent_title] => 'High density MOSFET with raised source and drain regions'
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Array
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[patent_title] => 'Buried strap for trench storage capacitors in dram trench cells'
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Array
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Array
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Array
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Array
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