Search

Jose L Couso

Examiner (ID: 6293, Phone: (571)272-7388 , Office: P/2667 )

Most Active Art Unit
2667
Art Unit(s)
2606, 2714, 2667, 2616, 2721, 2624, 2621
Total Applications
2714
Issued Applications
2159
Pending Applications
113
Abandoned Applications
442

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3934477 [patent_doc_number] => 05972723 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Enhanced thin film wiring net repair process' [patent_app_type] => 1 [patent_app_number] => 8/955204 [patent_app_country] => US [patent_app_date] => 1997-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 3141 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/972/05972723.pdf [firstpage_image] =>[orig_patent_app_number] => 955204 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/955204
Enhanced thin film wiring net repair process Oct 20, 1997 Issued
Array ( [id] => 4084678 [patent_doc_number] => 06025237 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Methods of forming field effect transistors having graded drain region doping profiles therein' [patent_app_type] => 1 [patent_app_number] => 8/947091 [patent_app_country] => US [patent_app_date] => 1997-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 6173 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/025/06025237.pdf [firstpage_image] =>[orig_patent_app_number] => 947091 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/947091
Methods of forming field effect transistors having graded drain region doping profiles therein Oct 7, 1997 Issued
Array ( [id] => 4107070 [patent_doc_number] => 06057171 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Methods for determining on-chip interconnect process parameters' [patent_app_type] => 1 [patent_app_number] => 8/937393 [patent_app_country] => US [patent_app_date] => 1997-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 31 [patent_no_of_words] => 11174 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/057/06057171.pdf [firstpage_image] =>[orig_patent_app_number] => 937393 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/937393
Methods for determining on-chip interconnect process parameters Sep 24, 1997 Issued
Array ( [id] => 4050802 [patent_doc_number] => 05943596 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Fabrication of a gate electrode stack using a patterned oxide layer' [patent_app_type] => 1 [patent_app_number] => 8/927097 [patent_app_country] => US [patent_app_date] => 1997-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 3689 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/943/05943596.pdf [firstpage_image] =>[orig_patent_app_number] => 927097 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/927097
Fabrication of a gate electrode stack using a patterned oxide layer Aug 28, 1997 Issued
Array ( [id] => 4190929 [patent_doc_number] => 06130105 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-10 [patent_title] => 'Deposition rate control on wafers with varying characteristics' [patent_app_type] => 1 [patent_app_number] => 8/927103 [patent_app_country] => US [patent_app_date] => 1997-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 5690 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/130/06130105.pdf [firstpage_image] =>[orig_patent_app_number] => 927103 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/927103
Deposition rate control on wafers with varying characteristics Aug 27, 1997 Issued
Array ( [id] => 4124404 [patent_doc_number] => 06127195 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Methods of forming an apparatus for engaging electrically conductive pads and method of forming a removable electrical interconnect apparatus' [patent_app_type] => 1 [patent_app_number] => 8/895764 [patent_app_country] => US [patent_app_date] => 1997-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 3753 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/127/06127195.pdf [firstpage_image] =>[orig_patent_app_number] => 895764 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/895764
Methods of forming an apparatus for engaging electrically conductive pads and method of forming a removable electrical interconnect apparatus Jul 16, 1997 Issued
Array ( [id] => 4070567 [patent_doc_number] => 05970351 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Production method for a MISFET, complementary MISFET' [patent_app_type] => 1 [patent_app_number] => 8/890826 [patent_app_country] => US [patent_app_date] => 1997-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 29 [patent_no_of_words] => 7568 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/970/05970351.pdf [firstpage_image] =>[orig_patent_app_number] => 890826 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/890826
Production method for a MISFET, complementary MISFET Jul 9, 1997 Issued
Array ( [id] => 4222403 [patent_doc_number] => 06010953 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-04 [patent_title] => 'Method for forming a semiconductor buried contact with a removable spacer' [patent_app_type] => 1 [patent_app_number] => 8/886707 [patent_app_country] => US [patent_app_date] => 1997-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 2690 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/010/06010953.pdf [firstpage_image] =>[orig_patent_app_number] => 886707 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/886707
Method for forming a semiconductor buried contact with a removable spacer Jun 30, 1997 Issued
Array ( [id] => 4070837 [patent_doc_number] => 06069055 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-30 [patent_title] => 'Fabricating method for semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/886859 [patent_app_country] => US [patent_app_date] => 1997-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 33 [patent_no_of_words] => 3848 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/069/06069055.pdf [firstpage_image] =>[orig_patent_app_number] => 886859 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/886859
Fabricating method for semiconductor device Jun 30, 1997 Issued
Array ( [id] => 4206972 [patent_doc_number] => 06027996 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Method of planarizing a pre-metal dielectric layer using chemical-mechanical polishing' [patent_app_type] => 1 [patent_app_number] => 8/885173 [patent_app_country] => US [patent_app_date] => 1997-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1202 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/027/06027996.pdf [firstpage_image] =>[orig_patent_app_number] => 885173 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/885173
Method of planarizing a pre-metal dielectric layer using chemical-mechanical polishing Jun 29, 1997 Issued
Array ( [id] => 4214442 [patent_doc_number] => 06110783 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-29 [patent_title] => 'Method for forming a notched gate oxide asymmetric MOS device' [patent_app_type] => 1 [patent_app_number] => 8/883829 [patent_app_country] => US [patent_app_date] => 1997-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 10965 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/110/06110783.pdf [firstpage_image] =>[orig_patent_app_number] => 883829 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/883829
Method for forming a notched gate oxide asymmetric MOS device Jun 26, 1997 Issued
Array ( [id] => 4085470 [patent_doc_number] => 06017789 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-25 [patent_title] => 'Method of forming a Ta.sub.2 O.sub.5 dielectric layer with amorphous diffusion barrier layer and method of forming a capacitor having a b. Ta.su2 O.sub.5 dielectric layer with amorphous diffusion barrier layer' [patent_app_type] => 1 [patent_app_number] => 8/881561 [patent_app_country] => US [patent_app_date] => 1997-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2152 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/017/06017789.pdf [firstpage_image] =>[orig_patent_app_number] => 881561 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/881561
Method of forming a Ta.sub.2 O.sub.5 dielectric layer with amorphous diffusion barrier layer and method of forming a capacitor having a b. Ta.su2 O.sub.5 dielectric layer with amorphous diffusion barrier layer Jun 23, 1997 Issued
Array ( [id] => 4191086 [patent_doc_number] => 06043129 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'High density MOSFET with raised source and drain regions' [patent_app_type] => 1 [patent_app_number] => 8/876540 [patent_app_country] => US [patent_app_date] => 1997-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 9686 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/043/06043129.pdf [firstpage_image] =>[orig_patent_app_number] => 876540 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/876540
High density MOSFET with raised source and drain regions Jun 8, 1997 Issued
Array ( [id] => 3945285 [patent_doc_number] => 05953607 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Buried strap for trench storage capacitors in dram trench cells' [patent_app_type] => 1 [patent_app_number] => 8/870336 [patent_app_country] => US [patent_app_date] => 1997-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 24 [patent_no_of_words] => 1845 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/953/05953607.pdf [firstpage_image] =>[orig_patent_app_number] => 870336 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/870336
Buried strap for trench storage capacitors in dram trench cells Jun 5, 1997 Issued
Array ( [id] => 3941980 [patent_doc_number] => 05946558 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Method of making ROM components' [patent_app_type] => 1 [patent_app_number] => 8/866130 [patent_app_country] => US [patent_app_date] => 1997-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 1465 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/946/05946558.pdf [firstpage_image] =>[orig_patent_app_number] => 866130 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/866130
Method of making ROM components May 29, 1997 Issued
Array ( [id] => 3942208 [patent_doc_number] => 05946573 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Self-aligned silicide (salicide) process for electrostatic discharge (ESD) protection' [patent_app_type] => 1 [patent_app_number] => 8/862427 [patent_app_country] => US [patent_app_date] => 1997-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 1943 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/946/05946573.pdf [firstpage_image] =>[orig_patent_app_number] => 862427 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/862427
Self-aligned silicide (salicide) process for electrostatic discharge (ESD) protection May 23, 1997 Issued
Array ( [id] => 3943685 [patent_doc_number] => 05998228 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Method of testing semiconductor' [patent_app_type] => 1 [patent_app_number] => 8/839759 [patent_app_country] => US [patent_app_date] => 1997-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 51 [patent_no_of_words] => 24574 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/998/05998228.pdf [firstpage_image] =>[orig_patent_app_number] => 839759 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/839759
Method of testing semiconductor Apr 14, 1997 Issued
Array ( [id] => 3943893 [patent_doc_number] => 05976956 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Method of controlling dopant concentrations using transient-enhanced diffusion prior to gate formation in a device' [patent_app_type] => 1 [patent_app_number] => 8/837936 [patent_app_country] => US [patent_app_date] => 1997-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 6727 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/976/05976956.pdf [firstpage_image] =>[orig_patent_app_number] => 837936 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/837936
Method of controlling dopant concentrations using transient-enhanced diffusion prior to gate formation in a device Apr 10, 1997 Issued
Array ( [id] => 3999731 [patent_doc_number] => 05950104 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Contact process using Y-contact etching' [patent_app_type] => 1 [patent_app_number] => 8/835575 [patent_app_country] => US [patent_app_date] => 1997-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2233 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/950/05950104.pdf [firstpage_image] =>[orig_patent_app_number] => 835575 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/835575
Contact process using Y-contact etching Apr 8, 1997 Issued
Array ( [id] => 3964956 [patent_doc_number] => 05885878 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-23 [patent_title] => 'Lateral trench MISFET and method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 8/829751 [patent_app_country] => US [patent_app_date] => 1997-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 26 [patent_no_of_words] => 10806 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/885/05885878.pdf [firstpage_image] =>[orig_patent_app_number] => 829751 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/829751
Lateral trench MISFET and method of manufacturing the same Mar 30, 1997 Issued
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