Jose L Couso

Array ( [id] => 4000786 [patent_doc_number] => 05858847 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Method for a lightly doped drain structure' [patent_app_type] => 1 [patent_app_number] => 8/827239 [patent_app_country] => US [patent_app_date] => 1997-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3210 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/858/05858847.pdf [firstpage_image] =>[orig_patent_app_number] => 827239 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3967421 [patent_doc_number] => 05956617 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Method of manufacturing a semiconductor device employing salicide technology' [patent_app_type] => 1 [patent_app_number] => 8/816183 [patent_app_country] => US [patent_app_date] => 1997-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 44 [patent_no_of_words] => 10713 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/956/05956617.pdf [firstpage_image] =>[orig_patent_app_number] => 816183 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3957691 [patent_doc_number] => 05930651 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Method of forming a semiconductor device having a plurality of cavity defined gating regions' [patent_app_type] => 1 [patent_app_number] => 8/814787 [patent_app_country] => US [patent_app_date] => 1997-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 14269 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930651.pdf [firstpage_image] =>[orig_patent_app_number] => 814787 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3936782 [patent_doc_number] => 05981301 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Regeneration method and apparatus of wafer and substrate' [patent_app_type] => 1 [patent_app_number] => 8/804732 [patent_app_country] => US [patent_app_date] => 1997-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4130 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/981/05981301.pdf [firstpage_image] =>[orig_patent_app_number] => 804732 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3935159 [patent_doc_number] => 05972768 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Method of manufacturing semiconductor device having low contact resistance' [patent_app_type] => 1 [patent_app_number] => 8/803193 [patent_app_country] => US [patent_app_date] => 1997-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 30 [patent_no_of_words] => 5772 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/972/05972768.pdf [firstpage_image] =>[orig_patent_app_number] => 803193 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4070288 [patent_doc_number] => 05970335 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-19 [patent_title] => 'Semiconductor processing method of forming complementary n-type doped and p-type doped active regions within a semiconductor substrate' [patent_app_type] => 1 [patent_app_number] => 8/797547 [patent_app_country] => US [patent_app_date] => 1997-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 3428 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/970/05970335.pdf [firstpage_image] =>[orig_patent_app_number] => 797547 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4238379 [patent_doc_number] => 06080649 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Fusible link in an integrated semiconductor circuit and process for producing the fusible link' [patent_app_type] => 1 [patent_app_number] => 8/780492 [patent_app_country] => US [patent_app_date] => 1997-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2405 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/080/06080649.pdf [firstpage_image] =>[orig_patent_app_number] => 780492 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4107135 [patent_doc_number] => 06022815 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-08 [patent_title] => 'Method of fabricating next-to-minimum-size transistor gate using mask-edge gate definition technique' [patent_app_type] => 1 [patent_app_number] => 8/775412 [patent_app_country] => US [patent_app_date] => 1996-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 28 [patent_no_of_words] => 3795 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/022/06022815.pdf [firstpage_image] =>[orig_patent_app_number] => 775412 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3976259 [patent_doc_number] => 05937296 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Memory cell that includes a vertical transistor and a trench capacitor' [patent_app_type] => 1 [patent_app_number] => 8/770962 [patent_app_country] => US [patent_app_date] => 1996-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 6155 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/937/05937296.pdf [firstpage_image] =>[orig_patent_app_number] => 770962 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4004088 [patent_doc_number] => 05960275 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Power MOSFET fabrication process to achieve enhanced ruggedness, cost savings, and product reliability' [patent_app_type] => 1 [patent_app_number] => 8/738544 [patent_app_country] => US [patent_app_date] => 1996-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4366 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/960/05960275.pdf [firstpage_image] =>[orig_patent_app_number] => 738544 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4016279 [patent_doc_number] => 05923971 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Reliable low resistance strap for trench storage DRAM cell using selective epitaxy' [patent_app_type] => 1 [patent_app_number] => 8/731940 [patent_app_country] => US [patent_app_date] => 1996-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 2160 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/923/05923971.pdf [firstpage_image] =>[orig_patent_app_number] => 731940 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3942571 [patent_doc_number] => 05946596 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Method for preventing polycide line deformation by polycide hardening' [patent_app_type] => 1 [patent_app_number] => 8/734624 [patent_app_country] => US [patent_app_date] => 1996-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 6 [patent_no_of_words] => 3576 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/946/05946596.pdf [firstpage_image] =>[orig_patent_app_number] => 734624 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3956815 [patent_doc_number] => 05930596 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Semiconductor component for vertical integration and manufacturing method' [patent_app_type] => 1 [patent_app_number] => 8/721980 [patent_app_country] => US [patent_app_date] => 1996-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2049 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930596.pdf [firstpage_image] =>[orig_patent_app_number] => 721980 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3925900 [patent_doc_number] => 05877049 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-02 [patent_title] => 'Method for forming advanced transistor structures with optimum short channel controls for high density/high performance integrated circuits' [patent_app_type] => 1 [patent_app_number] => 8/717981 [patent_app_country] => US [patent_app_date] => 1996-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3643 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 12 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/877/05877049.pdf [firstpage_image] =>[orig_patent_app_number] => 717981 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3994637 [patent_doc_number] => 05918153 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'High density electronic circuit and process for making' [patent_app_type] => 1 [patent_app_number] => 8/715659 [patent_app_country] => US [patent_app_date] => 1996-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2165 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/918/05918153.pdf [firstpage_image] =>[orig_patent_app_number] => 715659 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4207107 [patent_doc_number] => 06028005 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Methods for reducing electric fields during the fabrication of integrated circuit devices' [patent_app_type] => 1 [patent_app_number] => 8/711250 [patent_app_country] => US [patent_app_date] => 1996-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2103 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/028/06028005.pdf [firstpage_image] =>[orig_patent_app_number] => 711250 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3950412 [patent_doc_number] => 05899717 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-04 [patent_title] => 'Method for fabricating semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/686678 [patent_app_country] => US [patent_app_date] => 1996-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 45 [patent_no_of_words] => 4459 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/899/05899717.pdf [firstpage_image] =>[orig_patent_app_number] => 686678 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4003147 [patent_doc_number] => 06004873 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-21 [patent_title] => 'Method for reducing the pattern sensitivity of ozone assisted chemical vapor deposited (CVD) silicon oxide insulator layers' [patent_app_type] => 1 [patent_app_number] => 8/666160 [patent_app_country] => US [patent_app_date] => 1996-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 8459 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/004/06004873.pdf [firstpage_image] =>[orig_patent_app_number] => 666160 [rel_patent_id] =>[rel_patent_doc_number] =>)