
Joselito Sasis Baisa
Examiner (ID: 14973, Phone: (571)272-7132 , Office: P/2837 )
| Most Active Art Unit | 2837 |
| Art Unit(s) | 2832, 2837 |
| Total Applications | 1023 |
| Issued Applications | 636 |
| Pending Applications | 64 |
| Abandoned Applications | 346 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 20045692
[patent_doc_number] => 20250183914
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-06-05
[patent_title] => APPARATUS AND METHOD FOR CHANNEL CODING IN COMMUNICATION SYSTEM
[patent_app_type] => utility
[patent_app_number] => 18/977898
[patent_app_country] => US
[patent_app_date] => 2024-12-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 19177
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18977898
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/977898 | APPARATUS AND METHOD FOR CHANNEL CODING IN COMMUNICATION SYSTEM | Dec 10, 2024 | Pending |
Array
(
[id] => 19848063
[patent_doc_number] => 20250093414
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-03-20
[patent_title] => APPARATUS FOR TESTING A DEVICE UNDER TEST SEPARATING ERRORS WITHIN A RECEIVED PATTERN ASSOCIATED WITH DIFFERENT FUNCTIONAL BLOCKS OF A DEVICE UNDER TEST OR ASSOCIATED WITH DIFFERENT BLOCKS OF ONE OR MORE BITS, METHOD AND COMPUTER PROGRAM
[patent_app_type] => utility
[patent_app_number] => 18/971433
[patent_app_country] => US
[patent_app_date] => 2024-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 26845
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18971433
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/971433 | APPARATUS FOR TESTING A DEVICE UNDER TEST SEPARATING ERRORS WITHIN A RECEIVED PATTERN ASSOCIATED WITH DIFFERENT FUNCTIONAL BLOCKS OF A DEVICE UNDER TEST OR ASSOCIATED WITH DIFFERENT BLOCKS OF ONE OR MORE BITS, METHOD AND COMPUTER PROGRAM | Dec 5, 2024 | Pending |
Array
(
[id] => 20063104
[patent_doc_number] => 20250201326
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-06-19
[patent_title] => DIE-LEVEL BLOCK FAMILY ERROR AVOIDANCE
[patent_app_type] => utility
[patent_app_number] => 18/967199
[patent_app_country] => US
[patent_app_date] => 2024-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10738
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18967199
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/967199 | DIE-LEVEL BLOCK FAMILY ERROR AVOIDANCE | Dec 2, 2024 | Pending |
Array
(
[id] => 20500634
[patent_doc_number] => 20260030094
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2026-01-29
[patent_title] => DECODER, DECODING METHOD, MEMORY SYSTEM AND CONTROLLER
[patent_app_type] => utility
[patent_app_number] => 18/965734
[patent_app_country] => US
[patent_app_date] => 2024-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6202
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18965734
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/965734 | DECODER, DECODING METHOD, MEMORY SYSTEM AND CONTROLLER | Dec 1, 2024 | Pending |
Array
(
[id] => 19802592
[patent_doc_number] => 20250068517
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-02-27
[patent_title] => STORAGE DEVICE INCLUDING MAPPING MEMORY AND METHOD OF OPERATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/944088
[patent_app_country] => US
[patent_app_date] => 2024-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11662
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -2
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18944088
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/944088 | STORAGE DEVICE INCLUDING MAPPING MEMORY AND METHOD OF OPERATING THE SAME | Nov 11, 2024 | Pending |
Array
(
[id] => 20429320
[patent_doc_number] => 20250391413
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-12-25
[patent_title] => METHOD AND SYSTEM FOR CONCEALING PACKET LOSS IN A COMMUNICATION SYSTEM
[patent_app_type] => utility
[patent_app_number] => 18/926782
[patent_app_country] => US
[patent_app_date] => 2024-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4639
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18926782
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/926782 | METHOD AND SYSTEM FOR CONCEALING PACKET LOSS IN A COMMUNICATION SYSTEM | Oct 24, 2024 | Pending |
Array
(
[id] => 19774169
[patent_doc_number] => 20250055595
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-02-13
[patent_title] => METHODS AND APPARATUS FOR INFORMATION TRANSMISSION
[patent_app_type] => utility
[patent_app_number] => 18/926197
[patent_app_country] => US
[patent_app_date] => 2024-10-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 44904
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18926197
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/926197 | METHODS AND APPARATUS FOR INFORMATION TRANSMISSION | Oct 23, 2024 | Pending |
Array
(
[id] => 20086516
[patent_doc_number] => 20250216452
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-07-03
[patent_title] => DEVICE TESTING SYSTEM AND DEVICE TESTING METHOD
[patent_app_type] => utility
[patent_app_number] => 18/908945
[patent_app_country] => US
[patent_app_date] => 2024-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18908945
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/908945 | DEVICE TESTING SYSTEM AND DEVICE TESTING METHOD | Oct 7, 2024 | Pending |
Array
(
[id] => 20036975
[patent_doc_number] => 20250175197
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-05-29
[patent_title] => SIGNAL TRANSMITTING METHOD, ELECTRONIC DEVICE, AND COMMUNICATION SYSTEM
[patent_app_type] => utility
[patent_app_number] => 18/898590
[patent_app_country] => US
[patent_app_date] => 2024-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18898590
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/898590 | SIGNAL TRANSMITTING METHOD, ELECTRONIC DEVICE, AND COMMUNICATION SYSTEM | Sep 25, 2024 | Issued |
Array
(
[id] => 19689103
[patent_doc_number] => 20250007648
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-01-02
[patent_title] => Methods for Rapid Fault Recovery of Corrupted 5G/6G Messages
[patent_app_type] => utility
[patent_app_number] => 18/886683
[patent_app_country] => US
[patent_app_date] => 2024-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 23617
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18886683
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/886683 | Methods for Rapid Fault Recovery of Corrupted 5G/6G Messages | Sep 15, 2024 | Pending |
Array
(
[id] => 20596314
[patent_doc_number] => 12580037
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2026-03-17
[patent_title] => Adaptable charge loss scanning cadence in a memory sub-system
[patent_app_type] => utility
[patent_app_number] => 18/819530
[patent_app_country] => US
[patent_app_date] => 2024-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 4701
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18819530
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/819530 | Adaptable charge loss scanning cadence in a memory sub-system | Aug 28, 2024 | Issued |
Array
(
[id] => 19758850
[patent_doc_number] => 20250047415
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-02-06
[patent_title] => SYSTEMS AND METHODS OF LOW LATENCY DATA COMMUNICATION FOR PHYSICAL LINK LAYER RELIABILITY
[patent_app_type] => utility
[patent_app_number] => 18/818262
[patent_app_country] => US
[patent_app_date] => 2024-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 18742
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18818262
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/818262 | SYSTEMS AND METHODS OF LOW LATENCY DATA COMMUNICATION FOR PHYSICAL LINK LAYER RELIABILITY | Aug 27, 2024 | Pending |
Array
(
[id] => 19848924
[patent_doc_number] => 20250094275
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-03-20
[patent_title] => EFFICIENT SECURITY METADATA ENCODING IN ERROR CORRECTING CODE (ECC) MEMORY WITHOUT DEDICATED ECC BITS
[patent_app_type] => utility
[patent_app_number] => 18/808871
[patent_app_country] => US
[patent_app_date] => 2024-08-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7591
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18808871
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/808871 | EFFICIENT SECURITY METADATA ENCODING IN ERROR CORRECTING CODE (ECC) MEMORY WITHOUT DEDICATED ECC BITS | Aug 18, 2024 | Pending |
Array
(
[id] => 20635736
[patent_doc_number] => 12596610
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-04-07
[patent_title] => Parity data in dynamic random access memory (DRAM)
[patent_app_type] => utility
[patent_app_number] => 18/800272
[patent_app_country] => US
[patent_app_date] => 2024-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 0
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 53
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18800272
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/800272 | PARITY DATA IN DYNAMIC RANDOM ACCESS MEMORY (DRAM) | Aug 11, 2024 | Issued |
Array
(
[id] => 20339504
[patent_doc_number] => 20250343624
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-11-06
[patent_title] => Multi-Protocol Underlay Network Tracing
[patent_app_type] => utility
[patent_app_number] => 18/798580
[patent_app_country] => US
[patent_app_date] => 2024-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12747
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18798580
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/798580 | Multi-Protocol Underlay Network Tracing | Aug 7, 2024 | Pending |
Array
(
[id] => 20515314
[patent_doc_number] => 20260039417
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2026-02-05
[patent_title] => REDUNDANCY CONFIGURATIONS FOR NON-COHERENT TRANSMISSIONS BETWEEN NETWORK DEVICES
[patent_app_type] => utility
[patent_app_number] => 18/792419
[patent_app_country] => US
[patent_app_date] => 2024-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 26450
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18792419
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/792419 | REDUNDANCY CONFIGURATIONS FOR NON-COHERENT TRANSMISSIONS BETWEEN NETWORK DEVICES | Jul 31, 2024 | Pending |
Array
(
[id] => 20125003
[patent_doc_number] => 20250240034
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-07-24
[patent_title] => ENCODING METHOD, ENCODER AND DATA TRANSMISSION SYSTEM
[patent_app_type] => utility
[patent_app_number] => 18/790695
[patent_app_country] => US
[patent_app_date] => 2024-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16732
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 242
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18790695
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/790695 | ENCODING METHOD, ENCODER AND DATA TRANSMISSION SYSTEM | Jul 30, 2024 | Pending |
Array
(
[id] => 20635739
[patent_doc_number] => 12596613
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-04-07
[patent_title] => Distributed hybrid buffer for memory systems
[patent_app_type] => utility
[patent_app_number] => 18/785951
[patent_app_country] => US
[patent_app_date] => 2024-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 2628
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 241
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18785951
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/785951 | DISTRIBUTED HYBRID BUFFER FOR MEMORY SYSTEMS | Jul 25, 2024 | Pending |
Array
(
[id] => 19864639
[patent_doc_number] => 20250103425
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-03-27
[patent_title] => CYCLIC REDUNDANCY CHECK COMPARISON FOR ERROR DETECTION
[patent_app_type] => utility
[patent_app_number] => 18/774412
[patent_app_country] => US
[patent_app_date] => 2024-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15699
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18774412
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/774412 | CYCLIC REDUNDANCY CHECK COMPARISON FOR ERROR DETECTION | Jul 15, 2024 | Pending |
Array
(
[id] => 20507424
[patent_doc_number] => 12541702
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-02-03
[patent_title] => Maximizing circuit execution duty cycle by streaming gates
[patent_app_type] => utility
[patent_app_number] => 18/770347
[patent_app_country] => US
[patent_app_date] => 2024-07-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 1173
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 180
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18770347
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/770347 | Maximizing circuit execution duty cycle by streaming gates | Jul 10, 2024 | Issued |