Search

Joseph C. Nicely

Examiner (ID: 150, Phone: (571)270-3834 , Office: P/2813 )

Most Active Art Unit
2813
Art Unit(s)
2813
Total Applications
1136
Issued Applications
876
Pending Applications
104
Abandoned Applications
189

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19176322 [patent_doc_number] => 20240162296 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => SEMICONDUCTOR DIE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/497409 [patent_app_country] => US [patent_app_date] => 2023-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3412 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18497409 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/497409
SEMICONDUCTOR DIE AND METHOD OF MANUFACTURING THE SAME Oct 29, 2023 Pending
Array ( [id] => 19305683 [patent_doc_number] => 20240234263 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2024-07-11 [patent_title] => PACKAGED HIGH VOLTAGE MOSFET DEVICE WITH CONNECTION CLIP AND MANUFACTURING PROCESS THEREOF [patent_app_type] => utility [patent_app_number] => 18/493686 [patent_app_country] => US [patent_app_date] => 2023-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5881 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18493686 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/493686
PACKAGED HIGH VOLTAGE MOSFET DEVICE WITH CONNECTION CLIP AND MANUFACTURING PROCESS THEREOF Oct 23, 2023 Pending
Array ( [id] => 19305683 [patent_doc_number] => 20240234263 [patent_country] => US [patent_kind] => A9 [patent_issue_date] => 2024-07-11 [patent_title] => PACKAGED HIGH VOLTAGE MOSFET DEVICE WITH CONNECTION CLIP AND MANUFACTURING PROCESS THEREOF [patent_app_type] => utility [patent_app_number] => 18/493686 [patent_app_country] => US [patent_app_date] => 2023-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5881 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18493686 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/493686
PACKAGED HIGH VOLTAGE MOSFET DEVICE WITH CONNECTION CLIP AND MANUFACTURING PROCESS THEREOF Oct 22, 2023 Pending
Array ( [id] => 19733805 [patent_doc_number] => 12211807 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-28 [patent_title] => Semiconductor doped region with biased isolated members [patent_app_type] => utility [patent_app_number] => 18/490866 [patent_app_country] => US [patent_app_date] => 2023-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 30 [patent_no_of_words] => 12106 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18490866 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/490866
Semiconductor doped region with biased isolated members Oct 19, 2023 Issued
Array ( [id] => 19444677 [patent_doc_number] => 12094969 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Transistor device having a field plate [patent_app_type] => utility [patent_app_number] => 18/487505 [patent_app_country] => US [patent_app_date] => 2023-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 7721 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18487505 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/487505
Transistor device having a field plate Oct 15, 2023 Issued
Array ( [id] => 19176432 [patent_doc_number] => 20240162406 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => DISPLAY PANEL AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/480645 [patent_app_country] => US [patent_app_date] => 2023-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7280 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18480645 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/480645
DISPLAY PANEL AND MANUFACTURING METHOD THEREOF Oct 3, 2023 Pending
Array ( [id] => 19444530 [patent_doc_number] => 12094821 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Methods for forming semiconductor structures [patent_app_type] => utility [patent_app_number] => 18/467482 [patent_app_country] => US [patent_app_date] => 2023-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 3336 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18467482 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/467482
Methods for forming semiconductor structures Sep 13, 2023 Issued
Array ( [id] => 19269630 [patent_doc_number] => 20240213334 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => HIGH ELECTRON MOBILITY TRANSISTOR AND HIGH ELECTRON MOBILITY TRANSISTOR FORMING METHOD [patent_app_type] => utility [patent_app_number] => 18/466434 [patent_app_country] => US [patent_app_date] => 2023-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6588 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18466434 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/466434
HIGH ELECTRON MOBILITY TRANSISTOR AND HIGH ELECTRON MOBILITY TRANSISTOR FORMING METHOD Sep 12, 2023 Issued
Array ( [id] => 19796441 [patent_doc_number] => 12237413 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-25 [patent_title] => LDMOS with enhanced safe operating area and method of manufacture [patent_app_type] => utility [patent_app_number] => 18/447783 [patent_app_country] => US [patent_app_date] => 2023-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 8997 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18447783 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/447783
LDMOS with enhanced safe operating area and method of manufacture Aug 9, 2023 Issued
Array ( [id] => 20496660 [patent_doc_number] => 12538551 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-27 [patent_title] => Semiconductor structures for galvanic isolation [patent_app_type] => utility [patent_app_number] => 18/366711 [patent_app_country] => US [patent_app_date] => 2023-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 24 [patent_no_of_words] => 5158 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18366711 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/366711
Semiconductor structures for galvanic isolation Aug 7, 2023 Issued
Array ( [id] => 19414809 [patent_doc_number] => 12080646 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => Semiconductor structures and methods of forming the same [patent_app_type] => utility [patent_app_number] => 18/446113 [patent_app_country] => US [patent_app_date] => 2023-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 54 [patent_figures_cnt] => 54 [patent_no_of_words] => 10232 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18446113 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/446113
Semiconductor structures and methods of forming the same Aug 7, 2023 Issued
Array ( [id] => 20332807 [patent_doc_number] => 12463092 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Semiconductor device with air gaps and method of fabrication thereof [patent_app_type] => utility [patent_app_number] => 18/446183 [patent_app_country] => US [patent_app_date] => 2023-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 146 [patent_no_of_words] => 9045 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18446183 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/446183
Semiconductor device with air gaps and method of fabrication thereof Aug 7, 2023 Issued
Array ( [id] => 18812976 [patent_doc_number] => 20230387313 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => TRANSISTOR INCLUDING HYDROGEN DIFFUSION BARRIER FILM AND METHODS OF FORMING SAME [patent_app_type] => utility [patent_app_number] => 18/230864 [patent_app_country] => US [patent_app_date] => 2023-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10017 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18230864 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/230864
TRANSISTOR INCLUDING HYDROGEN DIFFUSION BARRIER FILM AND METHODS OF FORMING SAME Aug 6, 2023 Pending
Array ( [id] => 19407106 [patent_doc_number] => 20240290617 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => FIELD-EFFECT TRANSISTORS WITH A GATE DIELECTRIC LAYER FORMED ON A SURFACE TREATED BY ATOMIC LAYER ETCHING [patent_app_type] => utility [patent_app_number] => 18/228713 [patent_app_country] => US [patent_app_date] => 2023-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5783 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18228713 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/228713
FIELD-EFFECT TRANSISTORS WITH A GATE DIELECTRIC LAYER FORMED ON A SURFACE TREATED BY ATOMIC LAYER ETCHING Jul 31, 2023 Pending
Array ( [id] => 19452970 [patent_doc_number] => 20240313100 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/361647 [patent_app_country] => US [patent_app_date] => 2023-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6604 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18361647 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/361647
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME Jul 27, 2023 Pending
Array ( [id] => 19688156 [patent_doc_number] => 20250006701 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => SEMICONDUCTOR DIE STACKING ARCHITECTURE AND CONNECTION METHOD THEREFORE [patent_app_type] => utility [patent_app_number] => 18/360555 [patent_app_country] => US [patent_app_date] => 2023-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5852 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18360555 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/360555
SEMICONDUCTOR DIE STACKING ARCHITECTURE AND CONNECTION METHOD THEREFORE Jul 26, 2023 Pending
Array ( [id] => 20217663 [patent_doc_number] => 12414332 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-09 [patent_title] => Structure and method for semiconductor devices [patent_app_type] => utility [patent_app_number] => 18/360508 [patent_app_country] => US [patent_app_date] => 2023-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 167 [patent_no_of_words] => 7523 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18360508 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/360508
Structure and method for semiconductor devices Jul 26, 2023 Issued
Array ( [id] => 18757725 [patent_doc_number] => 20230361188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => THICKER CORNER OF A GATE DIELECTRIC STRUCTURE AROUND A RECESSED GATE ELECTRODE FOR AN MV DEVICE [patent_app_type] => utility [patent_app_number] => 18/355549 [patent_app_country] => US [patent_app_date] => 2023-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11693 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18355549 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/355549
Thicker corner of a gate dielectric structure around a recessed gate electrode for an MV device Jul 19, 2023 Issued
Array ( [id] => 18743317 [patent_doc_number] => 20230352305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/351149 [patent_app_country] => US [patent_app_date] => 2023-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7612 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18351149 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/351149
Semiconductor device and manufacturing method thereof Jul 11, 2023 Issued
Array ( [id] => 18743561 [patent_doc_number] => 20230352549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/348334 [patent_app_country] => US [patent_app_date] => 2023-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3701 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18348334 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/348334
Manufacturing method of semiconductor structure Jul 5, 2023 Issued
Menu