Search

Joseph C. Nicely

Examiner (ID: 16028, Phone: (571)270-3834 , Office: P/2813 )

Most Active Art Unit
2813
Art Unit(s)
2813
Total Applications
1158
Issued Applications
887
Pending Applications
98
Abandoned Applications
191

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12102305 [patent_doc_number] => 09859405 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-01-02 [patent_title] => 'Heterojunction bipolar transistor' [patent_app_type] => utility [patent_app_number] => 15/610711 [patent_app_country] => US [patent_app_date] => 2017-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 8220 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15610711 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/610711
Heterojunction bipolar transistor May 31, 2017 Issued
Array ( [id] => 13043035 [patent_doc_number] => 10043657 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-07 [patent_title] => Plasma assisted atomic layer deposition metal oxide for patterning applications [patent_app_type] => utility [patent_app_number] => 15/609864 [patent_app_country] => US [patent_app_date] => 2017-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 12952 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15609864 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/609864
Plasma assisted atomic layer deposition metal oxide for patterning applications May 30, 2017 Issued
Array ( [id] => 14110595 [patent_doc_number] => 20190096973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => METHOD FOR FABRICATING A TFT BACKPLANE AND TFT BACKPLANE [patent_app_type] => utility [patent_app_number] => 15/532493 [patent_app_country] => US [patent_app_date] => 2017-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4464 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15532493 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/532493
Method for fabricating a TFT backplane and TFT backplane May 11, 2017 Issued
Array ( [id] => 16249694 [patent_doc_number] => 10749070 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-18 [patent_title] => Method of forming a P-type layer for a light emitting device [patent_app_type] => utility [patent_app_number] => 15/592658 [patent_app_country] => US [patent_app_date] => 2017-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 5890 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15592658 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/592658
Method of forming a P-type layer for a light emitting device May 10, 2017 Issued
Array ( [id] => 12054454 [patent_doc_number] => 20170330797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-16 [patent_title] => 'MANGANESE BARRIER AND ADHESION LAYERS FOR COBALT' [patent_app_type] => utility [patent_app_number] => 15/592046 [patent_app_country] => US [patent_app_date] => 2017-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10145 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15592046 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/592046
Manganese barrier and adhesion layers for cobalt May 9, 2017 Issued
Array ( [id] => 13132013 [patent_doc_number] => 10083946 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-25 [patent_title] => Integrated fan-out structure with guiding trenches in buffer layer [patent_app_type] => utility [patent_app_number] => 15/495017 [patent_app_country] => US [patent_app_date] => 2017-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 3618 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15495017 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/495017
Integrated fan-out structure with guiding trenches in buffer layer Apr 23, 2017 Issued
Array ( [id] => 13499657 [patent_doc_number] => 20180301371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-18 [patent_title] => Contact Plugs and Methods Forming Same [patent_app_type] => utility [patent_app_number] => 15/490439 [patent_app_country] => US [patent_app_date] => 2017-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6120 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15490439 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/490439
Contact plugs and methods forming same Apr 17, 2017 Issued
Array ( [id] => 11760299 [patent_doc_number] => 20170207168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-20 [patent_title] => 'BRIDGE INTERCONNECTION WITH LAYERED INTERCONNECT STRUCTURES' [patent_app_type] => utility [patent_app_number] => 15/478858 [patent_app_country] => US [patent_app_date] => 2017-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8591 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15478858 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/478858
Bridge interconnection with layered interconnect structures Apr 3, 2017 Issued
Array ( [id] => 11997384 [patent_doc_number] => 20170301539 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-19 [patent_title] => 'METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM' [patent_app_type] => utility [patent_app_number] => 15/474138 [patent_app_country] => US [patent_app_date] => 2017-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 11582 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15474138 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/474138
Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium Mar 29, 2017 Issued
Array ( [id] => 14151455 [patent_doc_number] => 10256116 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-09 [patent_title] => Process for packaging circuit component having copper circuits with solid electrical and thermal conductivities and circuit component thereof [patent_app_type] => utility [patent_app_number] => 15/474332 [patent_app_country] => US [patent_app_date] => 2017-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 2758 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15474332 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/474332
Process for packaging circuit component having copper circuits with solid electrical and thermal conductivities and circuit component thereof Mar 29, 2017 Issued
Array ( [id] => 13769913 [patent_doc_number] => 10177307 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-08 [patent_title] => Methods of fabricating magnetic memory devices [patent_app_type] => utility [patent_app_number] => 15/474388 [patent_app_country] => US [patent_app_date] => 2017-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 44 [patent_no_of_words] => 7024 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15474388 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/474388
Methods of fabricating magnetic memory devices Mar 29, 2017 Issued
Array ( [id] => 13470407 [patent_doc_number] => 20180286746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-04 [patent_title] => SELECTIVE DEPOSITION OF WCN BARRIER/ADHESION LAYER FOR INTERCONNECT [patent_app_type] => utility [patent_app_number] => 15/474383 [patent_app_country] => US [patent_app_date] => 2017-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8249 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15474383 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/474383
Selective deposition of WCN barrier/adhesion layer for interconnect Mar 29, 2017 Issued
Array ( [id] => 12573774 [patent_doc_number] => 10020184 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-10 [patent_title] => Method for cleaning substrate [patent_app_type] => utility [patent_app_number] => 15/454134 [patent_app_country] => US [patent_app_date] => 2017-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6655 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15454134 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/454134
Method for cleaning substrate Mar 8, 2017 Issued
Array ( [id] => 11710414 [patent_doc_number] => 20170178913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'ASYMMETRIC HIGH-K DIELECTRIC FOR REDUCING GATE INDUCED DRAIN LEAKAGE' [patent_app_type] => utility [patent_app_number] => 15/450508 [patent_app_country] => US [patent_app_date] => 2017-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3423 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15450508 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/450508
Asymmetric high-k dielectric for reducing gate induced drain leakage Mar 5, 2017 Issued
Array ( [id] => 12154639 [patent_doc_number] => 20180025903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-25 [patent_title] => 'TOOLS & METHODS FOR PRODUCING NANOANTENNA ELECTRONIC DEVICES' [patent_app_type] => utility [patent_app_number] => 15/447807 [patent_app_country] => US [patent_app_date] => 2017-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8453 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15447807 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/447807
Tools and methods for producing nanoantenna electronic devices Mar 1, 2017 Issued
Array ( [id] => 13271057 [patent_doc_number] => 10147615 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-04 [patent_title] => Fabrication method of package structure [patent_app_type] => utility [patent_app_number] => 15/440390 [patent_app_country] => US [patent_app_date] => 2017-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 2720 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15440390 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/440390
Fabrication method of package structure Feb 22, 2017 Issued
Array ( [id] => 12554535 [patent_doc_number] => 10014403 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-03 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 15/437559 [patent_app_country] => US [patent_app_date] => 2017-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 44 [patent_no_of_words] => 18903 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15437559 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/437559
Semiconductor device Feb 20, 2017 Issued
Array ( [id] => 15200445 [patent_doc_number] => 10497725 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-03 [patent_title] => Method of producing display panel board [patent_app_type] => utility [patent_app_number] => 16/078280 [patent_app_country] => US [patent_app_date] => 2017-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9259 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16078280 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/078280
Method of producing display panel board Feb 16, 2017 Issued
Array ( [id] => 11652903 [patent_doc_number] => 20170148804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-25 [patent_title] => 'Three-Dimensionally Integrated Circuit Devices Including Oxidation Suppression Layers' [patent_app_type] => utility [patent_app_number] => 15/426081 [patent_app_country] => US [patent_app_date] => 2017-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 41 [patent_no_of_words] => 13637 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15426081 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/426081
Three-dimensionally integrated circuit devices including oxidation suppression layers Feb 6, 2017 Issued
Array ( [id] => 11652970 [patent_doc_number] => 20170148871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-25 [patent_title] => 'MOSFET HAVING DUAL-GATE CELLS WITH AN INTEGRATED CHANNEL DIODE' [patent_app_type] => utility [patent_app_number] => 15/423935 [patent_app_country] => US [patent_app_date] => 2017-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4958 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15423935 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/423935
MOSFET having dual-gate cells with an integrated channel diode Feb 2, 2017 Issued
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