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Joseph Clawson Jr.

Examiner (ID: 366)

Most Active Art Unit
2503
Art Unit(s)
2312, 2511, 2503, 2305, 2504, 2508, 2303, 2818
Total Applications
990
Issued Applications
627
Pending Applications
15
Abandoned Applications
348

Applications

Application numberTitle of the applicationFiling DateStatus
08/135695 LOW VOLTAGE FLASH EEPROM X-CELL USING FOWLER-NORDHEIM TUNNELING Oct 11, 1993 Abandoned
Array ( [id] => 3427929 [patent_doc_number] => 05434814 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-18 [patent_title] => 'Circuit for repairing defective read only memories with redundant NAND string' [patent_app_type] => 1 [patent_app_number] => 8/132175 [patent_app_country] => US [patent_app_date] => 1993-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3447 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/434/05434814.pdf [firstpage_image] =>[orig_patent_app_number] => 132175 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/132175
Circuit for repairing defective read only memories with redundant NAND string Oct 5, 1993 Issued
08/132444 DYNAMIC ASSOCIATIVE MEMORY WITH LOGIC-IN-REFRESH Oct 5, 1993 Abandoned
Array ( [id] => 3131151 [patent_doc_number] => 05384748 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-24 [patent_title] => 'Memory card with two SRAM arrays with different data holding voltages and power back-up' [patent_app_type] => 1 [patent_app_number] => 8/130876 [patent_app_country] => US [patent_app_date] => 1993-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3672 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/384/05384748.pdf [firstpage_image] =>[orig_patent_app_number] => 130876 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/130876
Memory card with two SRAM arrays with different data holding voltages and power back-up Oct 3, 1993 Issued
Array ( [id] => 3428459 [patent_doc_number] => 05479368 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-26 [patent_title] => 'Spacer flash cell device with vertically oriented floating gate' [patent_app_type] => 1 [patent_app_number] => 8/129866 [patent_app_country] => US [patent_app_date] => 1993-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 5024 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 314 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/479/05479368.pdf [firstpage_image] =>[orig_patent_app_number] => 129866 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/129866
Spacer flash cell device with vertically oriented floating gate Sep 29, 1993 Issued
08/127776 NONVOLATILE MEMORY WITH BLOCKS AND CIRCUITRY FOR SELECTIVELY PROTECTING THE BLOCKS FROM MEMORY OPERATIONS Sep 26, 1993 Abandoned
Array ( [id] => 3432895 [patent_doc_number] => 05422844 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-06 [patent_title] => 'Memory array with field oxide islands eliminated and method' [patent_app_type] => 1 [patent_app_number] => 8/126506 [patent_app_country] => US [patent_app_date] => 1993-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 4418 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/422/05422844.pdf [firstpage_image] =>[orig_patent_app_number] => 126506 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/126506
Memory array with field oxide islands eliminated and method Sep 23, 1993 Issued
08/126135 DYNAMIC RANDOM ACCESS MEMORY DEVICE Sep 22, 1993 Abandoned
Array ( [id] => 3432883 [patent_doc_number] => 05422843 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-06 [patent_title] => 'Method of erasing information in memory cells' [patent_app_type] => 1 [patent_app_number] => 8/123476 [patent_app_country] => US [patent_app_date] => 1993-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2416 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/422/05422843.pdf [firstpage_image] =>[orig_patent_app_number] => 123476 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/123476
Method of erasing information in memory cells Sep 19, 1993 Issued
Array ( [id] => 3039414 [patent_doc_number] => 05349554 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-20 [patent_title] => 'Memory element with bipolar transistors in resettable latch' [patent_app_type] => 1 [patent_app_number] => 8/123524 [patent_app_country] => US [patent_app_date] => 1993-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2714 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 534 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/349/05349554.pdf [firstpage_image] =>[orig_patent_app_number] => 123524 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/123524
Memory element with bipolar transistors in resettable latch Sep 16, 1993 Issued
Array ( [id] => 3076181 [patent_doc_number] => 05353251 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-04 [patent_title] => 'Memory cell circuit with single bit line latch' [patent_app_type] => 1 [patent_app_number] => 8/123434 [patent_app_country] => US [patent_app_date] => 1993-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3393 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/353/05353251.pdf [firstpage_image] =>[orig_patent_app_number] => 123434 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/123434
Memory cell circuit with single bit line latch Sep 15, 1993 Issued
Array ( [id] => 3025577 [patent_doc_number] => 05341337 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-23 [patent_title] => 'Semiconductor read only memory with paralleled selecting transistors for higher speed' [patent_app_type] => 1 [patent_app_number] => 8/121424 [patent_app_country] => US [patent_app_date] => 1993-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3201 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/341/05341337.pdf [firstpage_image] =>[orig_patent_app_number] => 121424 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/121424
Semiconductor read only memory with paralleled selecting transistors for higher speed Sep 15, 1993 Issued
Array ( [id] => 3469315 [patent_doc_number] => 05442586 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-15 [patent_title] => 'Method and apparatus for controlling the output current provided by a charge pump circuit' [patent_app_type] => 1 [patent_app_number] => 8/119425 [patent_app_country] => US [patent_app_date] => 1993-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5737 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/442/05442586.pdf [firstpage_image] =>[orig_patent_app_number] => 119425 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/119425
Method and apparatus for controlling the output current provided by a charge pump circuit Sep 9, 1993 Issued
Array ( [id] => 3024554 [patent_doc_number] => 05309394 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-03 [patent_title] => 'Single element security fusible link' [patent_app_type] => 1 [patent_app_number] => 8/118161 [patent_app_country] => US [patent_app_date] => 1993-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1556 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/309/05309394.pdf [firstpage_image] =>[orig_patent_app_number] => 118161 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/118161
Single element security fusible link Sep 7, 1993 Issued
08/116906 SEMICONDUCTOR MEMORY Sep 2, 1993 Abandoned
Array ( [id] => 3024449 [patent_doc_number] => 05309389 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-03 [patent_title] => 'Read-only memory with complementary data lines' [patent_app_type] => 1 [patent_app_number] => 8/112485 [patent_app_country] => US [patent_app_date] => 1993-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1656 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/309/05309389.pdf [firstpage_image] =>[orig_patent_app_number] => 112485 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/112485
Read-only memory with complementary data lines Aug 26, 1993 Issued
08/112393 WRITABLE ANALOG REFERENCE VOLTAGE STORAGE DEVICE Aug 25, 1993 Abandoned
Array ( [id] => 3009135 [patent_doc_number] => 05359558 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-25 [patent_title] => 'Flash eeprom array with improved high endurance' [patent_app_type] => 1 [patent_app_number] => 8/109886 [patent_app_country] => US [patent_app_date] => 1993-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6756 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/359/05359558.pdf [firstpage_image] =>[orig_patent_app_number] => 109886 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/109886
Flash eeprom array with improved high endurance Aug 22, 1993 Issued
08/109094 6-BULK TRANSISTOR STATIC MEMORY CELL USING SPLIT WORDLINE ARCHITECTURE Aug 18, 1993 Abandoned
08/098406 FLASH MEMORY WITH IMPROVED ERASABILITY AND ITS CIRCUITRY Aug 5, 1993 Pending
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