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Joseph D Harris

Examiner (ID: 6641)

Most Active Art Unit
3769
Art Unit(s)
3769
Total Applications
17
Issued Applications
4
Pending Applications
0
Abandoned Applications
13

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5907260 [patent_doc_number] => 20060048029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/206948 [patent_app_country] => US [patent_app_date] => 2005-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4180 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20060048029.pdf [firstpage_image] =>[orig_patent_app_number] => 11206948 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/206948
Semiconductor integrated circuit Aug 18, 2005 Issued
Array ( [id] => 5706692 [patent_doc_number] => 20060195740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-31 [patent_title] => 'Clock duty cycle based access timer combined with standard stage clocked output register' [patent_app_type] => utility [patent_app_number] => 11/057318 [patent_app_country] => US [patent_app_date] => 2005-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1350 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20060195740.pdf [firstpage_image] =>[orig_patent_app_number] => 11057318 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/057318
Clock duty cycle based access timer combined with standard stage clocked output register Feb 10, 2005 Issued
Array ( [id] => 5696001 [patent_doc_number] => 20060156148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-13 [patent_title] => 'Application specific integrated circuit with internal testing' [patent_app_type] => utility [patent_app_number] => 11/011232 [patent_app_country] => US [patent_app_date] => 2004-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4014 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20060156148.pdf [firstpage_image] =>[orig_patent_app_number] => 11011232 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/011232
Application specific integrated circuit with internal testing Dec 13, 2004 Issued
Array ( [id] => 6920104 [patent_doc_number] => 20050097410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'Memory device and input signal control method of a memory device' [patent_app_type] => utility [patent_app_number] => 10/975006 [patent_app_country] => US [patent_app_date] => 2004-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3933 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20050097410.pdf [firstpage_image] =>[orig_patent_app_number] => 10975006 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/975006
Memory device and input signal control method of a memory device Oct 27, 2004 Issued
Array ( [id] => 6936952 [patent_doc_number] => 20050110513 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-26 [patent_title] => 'Semiconductor test module and method of testing semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/969988 [patent_app_country] => US [patent_app_date] => 2004-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5535 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20050110513.pdf [firstpage_image] =>[orig_patent_app_number] => 10969988 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/969988
Semiconductor test module and method of testing semiconductor device Oct 21, 2004 Abandoned
Array ( [id] => 6920111 [patent_doc_number] => 20050097414 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'Apparatus and method for performing poll commands using JTAG scans' [patent_app_type] => utility [patent_app_number] => 10/966659 [patent_app_country] => US [patent_app_date] => 2004-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1975 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20050097414.pdf [firstpage_image] =>[orig_patent_app_number] => 10966659 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/966659
Apparatus and method for performing poll commands using JTAG scans Oct 14, 2004 Abandoned
Array ( [id] => 6927588 [patent_doc_number] => 20050240845 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-27 [patent_title] => 'Reducing Number of Pins Required to Test Integrated Circuits' [patent_app_type] => utility [patent_app_number] => 10/709238 [patent_app_country] => US [patent_app_date] => 2004-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3304 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0240/20050240845.pdf [firstpage_image] =>[orig_patent_app_number] => 10709238 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/709238
Reducing Number of Pins Required to Test Integrated Circuits Apr 22, 2004 Abandoned
Array ( [id] => 6927589 [patent_doc_number] => 20050240846 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-27 [patent_title] => 'Accurate Generation of Scan Enable Signal when Testing Integrated Circuits Using Sequential Scanning Techniques' [patent_app_type] => utility [patent_app_number] => 10/709240 [patent_app_country] => US [patent_app_date] => 2004-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5154 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0240/20050240846.pdf [firstpage_image] =>[orig_patent_app_number] => 10709240 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/709240
Accurate Generation of Scan Enable Signal when Testing Integrated Circuits Using Sequential Scanning Techniques Apr 22, 2004 Abandoned
Array ( [id] => 6953969 [patent_doc_number] => 20050229064 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-13 [patent_title] => 'Methods and systems for digital testing on automatic test equipment (ATE)' [patent_app_type] => utility [patent_app_number] => 10/822415 [patent_app_country] => US [patent_app_date] => 2004-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1986 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20050229064.pdf [firstpage_image] =>[orig_patent_app_number] => 10822415 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/822415
Methods and systems for digital testing on automatic test equipment (ATE) Apr 11, 2004 Abandoned
Array ( [id] => 7353862 [patent_doc_number] => 20040193983 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-30 [patent_title] => 'IC scan means changing output signals synchronous with clock signal' [patent_app_type] => new [patent_app_number] => 10/819336 [patent_app_country] => US [patent_app_date] => 2004-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 14521 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0193/20040193983.pdf [firstpage_image] =>[orig_patent_app_number] => 10819336 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/819336
IC scan means changing output signals synchronous with clock signal Apr 5, 2004 Abandoned
Array ( [id] => 469581 [patent_doc_number] => 07240253 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-03 [patent_title] => 'Semiconductor storage device' [patent_app_type] => utility [patent_app_number] => 10/817860 [patent_app_country] => US [patent_app_date] => 2004-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 13380 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 371 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/240/07240253.pdf [firstpage_image] =>[orig_patent_app_number] => 10817860 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/817860
Semiconductor storage device Apr 5, 2004 Issued
Array ( [id] => 435107 [patent_doc_number] => 07266742 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-09-04 [patent_title] => 'Method and apparatus for generating a local scan enable signal to test circuitry in a die' [patent_app_type] => utility [patent_app_number] => 10/819520 [patent_app_country] => US [patent_app_date] => 2004-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3013 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/266/07266742.pdf [firstpage_image] =>[orig_patent_app_number] => 10819520 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/819520
Method and apparatus for generating a local scan enable signal to test circuitry in a die Apr 5, 2004 Issued
Array ( [id] => 462555 [patent_doc_number] => 07246285 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-07-17 [patent_title] => 'Method of automatic fault isolation in a programmable logic device' [patent_app_type] => utility [patent_app_number] => 10/815492 [patent_app_country] => US [patent_app_date] => 2004-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 7228 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/246/07246285.pdf [firstpage_image] =>[orig_patent_app_number] => 10815492 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/815492
Method of automatic fault isolation in a programmable logic device Mar 31, 2004 Issued
Array ( [id] => 922612 [patent_doc_number] => 07321997 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-22 [patent_title] => 'Memory channel self test' [patent_app_type] => utility [patent_app_number] => 10/815217 [patent_app_country] => US [patent_app_date] => 2004-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8749 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/321/07321997.pdf [firstpage_image] =>[orig_patent_app_number] => 10815217 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/815217
Memory channel self test Mar 29, 2004 Issued
Array ( [id] => 623411 [patent_doc_number] => 07143329 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-11-28 [patent_title] => 'FPGA configuration memory with built-in error correction mechanism' [patent_app_type] => utility [patent_app_number] => 10/796475 [patent_app_country] => US [patent_app_date] => 2004-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7010 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/143/07143329.pdf [firstpage_image] =>[orig_patent_app_number] => 10796475 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/796475
FPGA configuration memory with built-in error correction mechanism Mar 8, 2004 Issued
Array ( [id] => 388766 [patent_doc_number] => 07305603 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-12-04 [patent_title] => 'Boundary scan cell and methods for integrating and operating the same' [patent_app_type] => utility [patent_app_number] => 10/762799 [patent_app_country] => US [patent_app_date] => 2004-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4912 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/305/07305603.pdf [firstpage_image] =>[orig_patent_app_number] => 10762799 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/762799
Boundary scan cell and methods for integrating and operating the same Jan 20, 2004 Issued
Array ( [id] => 381172 [patent_doc_number] => 07310752 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-18 [patent_title] => 'System and method for on-board timing margin testing of memory modules' [patent_app_type] => utility [patent_app_number] => 10/660844 [patent_app_country] => US [patent_app_date] => 2003-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6188 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/310/07310752.pdf [firstpage_image] =>[orig_patent_app_number] => 10660844 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/660844
System and method for on-board timing margin testing of memory modules Sep 11, 2003 Issued
Array ( [id] => 7085038 [patent_doc_number] => 20050050418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-03 [patent_title] => 'Method and apparatus for generating signal transitions used for testing an electronic device' [patent_app_type] => utility [patent_app_number] => 10/651168 [patent_app_country] => US [patent_app_date] => 2003-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5104 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20050050418.pdf [firstpage_image] =>[orig_patent_app_number] => 10651168 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/651168
Method and apparatus for generating signal transitions used for testing an electronic device Aug 27, 2003 Issued
Array ( [id] => 7361113 [patent_doc_number] => 20040049723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-11 [patent_title] => 'Semiconductor integrated circuit with a test circuit' [patent_app_type] => new [patent_app_number] => 10/649765 [patent_app_country] => US [patent_app_date] => 2003-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4152 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20040049723.pdf [firstpage_image] =>[orig_patent_app_number] => 10649765 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/649765
Semiconductor integrated circuit with a test circuit Aug 27, 2003 Issued
Array ( [id] => 659522 [patent_doc_number] => 07111210 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-19 [patent_title] => 'Accelerated test method for ferroelectric memory device' [patent_app_type] => utility [patent_app_number] => 10/632960 [patent_app_country] => US [patent_app_date] => 2003-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4907 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/111/07111210.pdf [firstpage_image] =>[orig_patent_app_number] => 10632960 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/632960
Accelerated test method for ferroelectric memory device Aug 3, 2003 Issued
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