Joseph D. Torres

Array ( [id] => 20236530 [patent_doc_number] => 20250293849 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-18 [patent_title] => MULTI-STAGE BURST DETECTION FOR COMMUNICATIONS SYSTEMS [patent_app_type] => utility [patent_app_number] => 19/062163 [patent_app_country] => US [patent_app_date] => 2025-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6355 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19062163 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19848064 [patent_doc_number] => 20250093415 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => METHOD AND SYSTEM FOR CONTROLLING ACTIONS OF TESTBENCH COMPONENTS WITHIN A TEST ENVIRONMENT [patent_app_type] => utility [patent_app_number] => 18/963847 [patent_app_country] => US [patent_app_date] => 2024-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9374 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18963847 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20883870 [patent_doc_number] => 12699913 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-08-04 [patent_title] => Computing platform with heterogenous quantum processors [patent_app_type] => utility [patent_app_number] => 18/953748 [patent_app_country] => US [patent_app_date] => 2024-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 2273 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18953748 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20696069 [patent_doc_number] => 20260127481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-05-07 [patent_title] => PARALLEL DECODING FOR QUANTUM ERROR CORRECTING CODES [patent_app_type] => utility [patent_app_number] => 18/952829 [patent_app_country] => US [patent_app_date] => 2024-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6261 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18952829 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19804877 [patent_doc_number] => 20250070802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => RECOVERING SCRAMBLING SEQUENCE INITIALIZATION FROM FROZEN BITS OF AN UNCODED DOWNLINK CONTROL INFORMATION VECTOR [patent_app_type] => utility [patent_app_number] => 18/946175 [patent_app_country] => US [patent_app_date] => 2024-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7711 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18946175 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19787234 [patent_doc_number] => 20250060913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => MEMORY DEVICE, MEMORY MODULE INCLUDING THE MEMORY DEVICE, AND OPERATING METHOD OF MEMORY CONTROLLER [patent_app_type] => utility [patent_app_number] => 18/938050 [patent_app_country] => US [patent_app_date] => 2024-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8822 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18938050 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20488952 [patent_doc_number] => 20260025154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-22 [patent_title] => APPARATUS FOR CANCELING NOISE FROM BROADCAST SIGNAL FOR ELECTRIC VEHICLE [patent_app_type] => utility [patent_app_number] => 19/134442 [patent_app_country] => US [patent_app_date] => 2024-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19134442 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20234353 [patent_doc_number] => 20250291672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-18 [patent_title] => DIRECT MEMORY ACCESS CONTROLLER FOR DETECTING TRANSIENT FAULTS [patent_app_type] => utility [patent_app_number] => 18/924562 [patent_app_country] => US [patent_app_date] => 2024-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3296 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18924562 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19758847 [patent_doc_number] => 20250047412 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => SIGNAL PROCESSING METHOD AND APPARATUS [patent_app_type] => utility [patent_app_number] => 18/924205 [patent_app_country] => US [patent_app_date] => 2024-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7799 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18924205 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20661004 [patent_doc_number] => 20260113058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-23 [patent_title] => DECODER CIRCUIT AND DECODING METHOD CAPABLE OF REDUCING NUMBER OF READ/WRITE OF MEMORY TO REDUCE POWER CONSUMPTION [patent_app_type] => utility [patent_app_number] => 18/919356 [patent_app_country] => US [patent_app_date] => 2024-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18919356 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20250890 [patent_doc_number] => 20250299759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => STORAGE DEVICE INCLUDING REDUNDANCY MEMORY CELL AND REPAIR METHOD OF FAIL MEMORY CELL INCLUDED IN STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/916318 [patent_app_country] => US [patent_app_date] => 2024-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3486 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18916318 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19725242 [patent_doc_number] => 20250027993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => INTEGRATED CIRCUIT INCLUDING CONSTANT-0 FLIP FLOPS RECONFIGURED TO PROVIDE OBSERVABLE AND CONTROLLABLE TEST POINTS [patent_app_type] => utility [patent_app_number] => 18/909760 [patent_app_country] => US [patent_app_date] => 2024-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5713 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18909760 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19713442 [patent_doc_number] => 20250023584 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => PMD-TO-TC-MAC INTERFACE WITH 2-STAGE FEC PROTECTION [patent_app_type] => utility [patent_app_number] => 18/896779 [patent_app_country] => US [patent_app_date] => 2024-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7814 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18896779 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19685495 [patent_doc_number] => 20250004040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => VIRTUAL MACHINE TESTING OF ELECTRICAL MACHINES USING PHYSICAL DOMAIN PERFORMANCE SIGNATURES [patent_app_type] => utility [patent_app_number] => 18/885819 [patent_app_country] => US [patent_app_date] => 2024-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14492 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18885819 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20513275 [patent_doc_number] => 20260037376 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-05 [patent_title] => METHODS, APPARATUSES, AND SYSTEMS FOR MANAGING PARITY DATA GENERATION IN A MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/885169 [patent_app_country] => US [patent_app_date] => 2024-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7874 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18885169 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19836416 [patent_doc_number] => 20250088202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-13 [patent_title] => Error Correction Device and Method for Correcting a Data Block [patent_app_type] => utility [patent_app_number] => 18/883373 [patent_app_country] => US [patent_app_date] => 2024-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7583 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18883373 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20589332 [patent_doc_number] => 20260074929 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-12 [patent_title] => DYNAMIC COMMUNICATION SCHEME SWITCHING [patent_app_type] => utility [patent_app_number] => 18/830487 [patent_app_country] => US [patent_app_date] => 2024-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11885 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18830487 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20806529 [patent_doc_number] => 12671444 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-30 [patent_title] => Arithmetic circuit, memory system, and method of controlling nonvolatile memory [patent_app_type] => utility [patent_app_number] => 18/825077 [patent_app_country] => US [patent_app_date] => 2024-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 7567 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 328 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18825077 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20125005 [patent_doc_number] => 20250240036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-24 [patent_title] => HARDWARE OPTIMIZATION DEVICE AND METHOD FOR LOW-DENSITY PARITY CHECK DECODER [patent_app_type] => utility [patent_app_number] => 18/823609 [patent_app_country] => US [patent_app_date] => 2024-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18823609 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20353448 [patent_doc_number] => 20250350300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-13 [patent_title] => Estimating Long-Term Block Error Rate of a Forward Error Correction Code [patent_app_type] => utility [patent_app_number] => 18/817275 [patent_app_country] => US [patent_app_date] => 2024-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18817275 [rel_patent_id] =>[rel_patent_doc_number] =>)