Search

Joseph D. Torres

Examiner (ID: 7353, Phone: (571)272-3829 , Office: P/2112 )

Most Active Art Unit
2112
Art Unit(s)
2112, 2133
Total Applications
2119
Issued Applications
1664
Pending Applications
97
Abandoned Applications
378

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20488952 [patent_doc_number] => 20260025154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-22 [patent_title] => APPARATUS FOR CANCELING NOISE FROM BROADCAST SIGNAL FOR ELECTRIC VEHICLE [patent_app_type] => utility [patent_app_number] => 19/134442 [patent_app_country] => US [patent_app_date] => 2024-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19134442 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/134442
APPARATUS FOR CANCELING NOISE FROM BROADCAST SIGNAL FOR ELECTRIC VEHICLE Nov 4, 2024 Pending
Array ( [id] => 20234353 [patent_doc_number] => 20250291672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-18 [patent_title] => DIRECT MEMORY ACCESS CONTROLLER FOR DETECTING TRANSIENT FAULTS [patent_app_type] => utility [patent_app_number] => 18/924562 [patent_app_country] => US [patent_app_date] => 2024-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3296 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18924562 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/924562
DIRECT MEMORY ACCESS CONTROLLER FOR DETECTING TRANSIENT FAULTS Oct 22, 2024 Pending
Array ( [id] => 19758847 [patent_doc_number] => 20250047412 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => SIGNAL PROCESSING METHOD AND APPARATUS [patent_app_type] => utility [patent_app_number] => 18/924205 [patent_app_country] => US [patent_app_date] => 2024-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7799 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18924205 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/924205
SIGNAL PROCESSING METHOD AND APPARATUS Oct 22, 2024 Pending
Array ( [id] => 20250890 [patent_doc_number] => 20250299759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => STORAGE DEVICE INCLUDING REDUNDANCY MEMORY CELL AND REPAIR METHOD OF FAIL MEMORY CELL INCLUDED IN STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/916318 [patent_app_country] => US [patent_app_date] => 2024-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3486 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18916318 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/916318
STORAGE DEVICE INCLUDING REDUNDANCY MEMORY CELL AND REPAIR METHOD OF FAIL MEMORY CELL INCLUDED IN STORAGE DEVICE Oct 14, 2024 Pending
Array ( [id] => 19725242 [patent_doc_number] => 20250027993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => INTEGRATED CIRCUIT INCLUDING CONSTANT-0 FLIP FLOPS RECONFIGURED TO PROVIDE OBSERVABLE AND CONTROLLABLE TEST POINTS [patent_app_type] => utility [patent_app_number] => 18/909760 [patent_app_country] => US [patent_app_date] => 2024-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5713 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18909760 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/909760
INTEGRATED CIRCUIT INCLUDING CONSTANT-0 FLIP FLOPS RECONFIGURED TO PROVIDE OBSERVABLE AND CONTROLLABLE TEST POINTS Oct 7, 2024 Pending
Array ( [id] => 19713442 [patent_doc_number] => 20250023584 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => PMD-TO-TC-MAC INTERFACE WITH 2-STAGE FEC PROTECTION [patent_app_type] => utility [patent_app_number] => 18/896779 [patent_app_country] => US [patent_app_date] => 2024-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7814 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18896779 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/896779
PMD-TO-TC-MAC INTERFACE WITH 2-STAGE FEC PROTECTION Sep 24, 2024 Pending
Array ( [id] => 19685495 [patent_doc_number] => 20250004040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => VIRTUAL MACHINE TESTING OF ELECTRICAL MACHINES USING PHYSICAL DOMAIN PERFORMANCE SIGNATURES [patent_app_type] => utility [patent_app_number] => 18/885819 [patent_app_country] => US [patent_app_date] => 2024-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14492 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18885819 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/885819
VIRTUAL MACHINE TESTING OF ELECTRICAL MACHINES USING PHYSICAL DOMAIN PERFORMANCE SIGNATURES Sep 15, 2024 Pending
Array ( [id] => 19836416 [patent_doc_number] => 20250088202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-13 [patent_title] => Error Correction Device and Method for Correcting a Data Block [patent_app_type] => utility [patent_app_number] => 18/883373 [patent_app_country] => US [patent_app_date] => 2024-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7583 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18883373 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/883373
Error Correction Device and Method for Correcting a Data Block Sep 11, 2024 Pending
Array ( [id] => 20221655 [patent_doc_number] => 20250284586 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-11 [patent_title] => ARITHMETIC CIRCUIT, MEMORY SYSTEM, AND METHOD OF CONTROLLING NONVOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 18/825077 [patent_app_country] => US [patent_app_date] => 2024-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7567 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 328 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18825077 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/825077
ARITHMETIC CIRCUIT, MEMORY SYSTEM, AND METHOD OF CONTROLLING NONVOLATILE MEMORY Sep 4, 2024 Pending
Array ( [id] => 20125005 [patent_doc_number] => 20250240036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-24 [patent_title] => HARDWARE OPTIMIZATION DEVICE AND METHOD FOR LOW-DENSITY PARITY CHECK DECODER [patent_app_type] => utility [patent_app_number] => 18/823609 [patent_app_country] => US [patent_app_date] => 2024-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18823609 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/823609
HARDWARE OPTIMIZATION DEVICE AND METHOD FOR LOW-DENSITY PARITY CHECK DECODER Sep 2, 2024 Pending
Array ( [id] => 20353448 [patent_doc_number] => 20250350300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-13 [patent_title] => Estimating Long-Term Block Error Rate of a Forward Error Correction Code [patent_app_type] => utility [patent_app_number] => 18/817275 [patent_app_country] => US [patent_app_date] => 2024-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18817275 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/817275
Estimating Long-Term Block Error Rate of a Forward Error Correction Code Aug 27, 2024 Pending
Array ( [id] => 19645022 [patent_doc_number] => 20240419542 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => COMMAND ADDRESS FAULT DETECTION [patent_app_type] => utility [patent_app_number] => 18/817713 [patent_app_country] => US [patent_app_date] => 2024-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11274 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18817713 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/817713
COMMAND ADDRESS FAULT DETECTION Aug 27, 2024 Pending
Array ( [id] => 19605788 [patent_doc_number] => 20240396668 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => COMMUNICATION DEVICE AND COMMUNICATION METHOD [patent_app_type] => utility [patent_app_number] => 18/795412 [patent_app_country] => US [patent_app_date] => 2024-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21157 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18795412 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/795412
COMMUNICATION DEVICE AND COMMUNICATION METHOD Aug 5, 2024 Pending
Array ( [id] => 20502373 [patent_doc_number] => 20260031836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-29 [patent_title] => LOW-DENSITY PARITY CHECK (LDPC) DECODERS USING PARTIAL SYNDROME EARLY TERMINATION [patent_app_type] => utility [patent_app_number] => 18/785976 [patent_app_country] => US [patent_app_date] => 2024-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10713 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18785976 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/785976
LOW-DENSITY PARITY CHECK (LDPC) DECODERS USING PARTIAL SYNDROME EARLY TERMINATION Jul 25, 2024 Pending
Array ( [id] => 20089721 [patent_doc_number] => 20250219657 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => METHOD AND DEVICE FOR SIMPLIFIED SUCCESSIVE CANCELLATION LIST DECODING OF POLARIZATION-ADJUSTED CONVOLUTIONAL (PAC) CODES [patent_app_type] => utility [patent_app_number] => 18/784446 [patent_app_country] => US [patent_app_date] => 2024-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7387 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18784446 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/784446
METHOD AND DEVICE FOR SIMPLIFIED SUCCESSIVE CANCELLATION LIST DECODING OF POLARIZATION-ADJUSTED CONVOLUTIONAL (PAC) CODES Jul 24, 2024 Pending
Array ( [id] => 19725622 [patent_doc_number] => 20250028373 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => VOLTAGE SCALING BASED ON ERROR RATE [patent_app_type] => utility [patent_app_number] => 18/773178 [patent_app_country] => US [patent_app_date] => 2024-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12447 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18773178 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/773178
VOLTAGE SCALING BASED ON ERROR RATE Jul 14, 2024 Pending
Array ( [id] => 20597084 [patent_doc_number] => 12580814 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-17 [patent_title] => Adapting forward error correction (FEC) or link parameters for improved post-FEC performance [patent_app_type] => utility [patent_app_number] => 18/770877 [patent_app_country] => US [patent_app_date] => 2024-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 11041 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18770877 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/770877
Adapting forward error correction (FEC) or link parameters for improved post-FEC performance Jul 11, 2024 Issued
Array ( [id] => 19934881 [patent_doc_number] => 12308089 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-20 [patent_title] => Semiconductor memory devices [patent_app_type] => utility [patent_app_number] => 18/771859 [patent_app_country] => US [patent_app_date] => 2024-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 31 [patent_no_of_words] => 9397 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18771859 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/771859
Semiconductor memory devices Jul 11, 2024 Issued
Array ( [id] => 20188517 [patent_doc_number] => 12399629 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-26 [patent_title] => Storage system having a host that manages physical data locations of a storage device [patent_app_type] => utility [patent_app_number] => 18/767906 [patent_app_country] => US [patent_app_date] => 2024-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 24 [patent_no_of_words] => 8146 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18767906 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/767906
Storage system having a host that manages physical data locations of a storage device Jul 8, 2024 Issued
Array ( [id] => 20176434 [patent_doc_number] => 12395194 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-19 [patent_title] => Method and apparatus for low-density parity-check (LDPC) coding [patent_app_type] => utility [patent_app_number] => 18/763594 [patent_app_country] => US [patent_app_date] => 2024-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 39 [patent_no_of_words] => 25193 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18763594 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/763594
Method and apparatus for low-density parity-check (LDPC) coding Jul 2, 2024 Issued
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