Search

Joseph D Torres

Examiner (ID: 7553, Phone: (571)272-3829 , Office: P/2112 )

Most Active Art Unit
2112
Art Unit(s)
2133, 2112
Total Applications
2010
Issued Applications
1547
Pending Applications
94
Abandoned Applications
368

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7634982 [patent_doc_number] => 06381684 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-30 [patent_title] => 'Quad data rate RAM' [patent_app_type] => B1 [patent_app_number] => 09/300758 [patent_app_country] => US [patent_app_date] => 1999-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5754 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/381/06381684.pdf [firstpage_image] =>[orig_patent_app_number] => 09300758 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/300758
Quad data rate RAM Apr 25, 1999 Issued
09/298439 SYSTEM AND METHOD FOR FLEXIBLE MEMORY BANKING Apr 22, 1999 Abandoned
Array ( [id] => 4312123 [patent_doc_number] => 06237060 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Cache management techniques' [patent_app_type] => 1 [patent_app_number] => 9/298628 [patent_app_country] => US [patent_app_date] => 1999-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5752 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/237/06237060.pdf [firstpage_image] =>[orig_patent_app_number] => 298628 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/298628
Cache management techniques Apr 22, 1999 Issued
Array ( [id] => 4399415 [patent_doc_number] => 06295595 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Method and structure for accessing a reduced address space of a defective memory' [patent_app_type] => 1 [patent_app_number] => 9/295934 [patent_app_country] => US [patent_app_date] => 1999-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 32 [patent_no_of_words] => 6861 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/295/06295595.pdf [firstpage_image] =>[orig_patent_app_number] => 295934 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/295934
Method and structure for accessing a reduced address space of a defective memory Apr 20, 1999 Issued
Array ( [id] => 1431401 [patent_doc_number] => 06519677 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-11 [patent_title] => 'Managing access to shared data in data processing networks' [patent_app_type] => B1 [patent_app_number] => 09/295734 [patent_app_country] => US [patent_app_date] => 1999-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4534 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/519/06519677.pdf [firstpage_image] =>[orig_patent_app_number] => 09295734 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/295734
Managing access to shared data in data processing networks Apr 19, 1999 Issued
Array ( [id] => 4366188 [patent_doc_number] => 06286082 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Apparatus and method to prevent overwriting of modified cache entries prior to write back' [patent_app_type] => 1 [patent_app_number] => 9/294939 [patent_app_country] => US [patent_app_date] => 1999-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6096 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/286/06286082.pdf [firstpage_image] =>[orig_patent_app_number] => 294939 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/294939
Apparatus and method to prevent overwriting of modified cache entries prior to write back Apr 18, 1999 Issued
Array ( [id] => 4325355 [patent_doc_number] => 06253284 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Memory module controlling system' [patent_app_type] => 1 [patent_app_number] => 9/246760 [patent_app_country] => US [patent_app_date] => 1999-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3403 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/253/06253284.pdf [firstpage_image] =>[orig_patent_app_number] => 246760 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/246760
Memory module controlling system Feb 7, 1999 Issued
Array ( [id] => 1339299 [patent_doc_number] => 06601151 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-29 [patent_title] => 'Apparatus and method for handling memory access requests in a data processing system' [patent_app_type] => B1 [patent_app_number] => 09/246614 [patent_app_country] => US [patent_app_date] => 1999-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 6990 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/601/06601151.pdf [firstpage_image] =>[orig_patent_app_number] => 09246614 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/246614
Apparatus and method for handling memory access requests in a data processing system Feb 7, 1999 Issued
Array ( [id] => 1567425 [patent_doc_number] => 06363457 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Method and system for non-disruptive addition and deletion of logical devices' [patent_app_type] => B1 [patent_app_number] => 09/246540 [patent_app_country] => US [patent_app_date] => 1999-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3097 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/363/06363457.pdf [firstpage_image] =>[orig_patent_app_number] => 09246540 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/246540
Method and system for non-disruptive addition and deletion of logical devices Feb 7, 1999 Issued
Array ( [id] => 6532017 [patent_doc_number] => 20020026566 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-28 [patent_title] => 'DATA BACKUP IN NON-VOLATILE MEMORY' [patent_app_type] => new [patent_app_number] => 09/245809 [patent_app_country] => US [patent_app_date] => 1999-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12745 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20020026566.pdf [firstpage_image] =>[orig_patent_app_number] => 09245809 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/245809
DATA BACKUP IN NON-VOLATILE MEMORY Feb 4, 1999 Abandoned
Array ( [id] => 4147483 [patent_doc_number] => 06128702 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Integrated processor/memory device with victim data cache' [patent_app_type] => 1 [patent_app_number] => 9/227133 [patent_app_country] => US [patent_app_date] => 1999-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9688 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/128/06128702.pdf [firstpage_image] =>[orig_patent_app_number] => 227133 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/227133
Integrated processor/memory device with victim data cache Jan 7, 1999 Issued
Array ( [id] => 4162331 [patent_doc_number] => 06032230 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Method and apparatus that detects and tolerates inconsistencies between the cache and main memory, and the translation lookaside buffer and the virtual memory page table in main memory' [patent_app_type] => 1 [patent_app_number] => 9/221535 [patent_app_country] => US [patent_app_date] => 1998-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5112 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/032/06032230.pdf [firstpage_image] =>[orig_patent_app_number] => 221535 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/221535
Method and apparatus that detects and tolerates inconsistencies between the cache and main memory, and the translation lookaside buffer and the virtual memory page table in main memory Dec 27, 1998 Issued
Array ( [id] => 4402204 [patent_doc_number] => 06279081 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'System and method for performing memory fetches for an ATM card' [patent_app_type] => 1 [patent_app_number] => 9/218226 [patent_app_country] => US [patent_app_date] => 1998-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 6977 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/279/06279081.pdf [firstpage_image] =>[orig_patent_app_number] => 218226 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/218226
System and method for performing memory fetches for an ATM card Dec 21, 1998 Issued
Array ( [id] => 4346388 [patent_doc_number] => 06330645 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Multi-stream coherent memory controller apparatus and method' [patent_app_type] => 1 [patent_app_number] => 9/217139 [patent_app_country] => US [patent_app_date] => 1998-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5878 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/330/06330645.pdf [firstpage_image] =>[orig_patent_app_number] => 217139 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/217139
Multi-stream coherent memory controller apparatus and method Dec 20, 1998 Issued
Array ( [id] => 4402401 [patent_doc_number] => 06279095 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Method and apparatus for omnibus wiring of virtual mapping table entries' [patent_app_type] => 1 [patent_app_number] => 9/189601 [patent_app_country] => US [patent_app_date] => 1998-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 9895 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/279/06279095.pdf [firstpage_image] =>[orig_patent_app_number] => 189601 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/189601
Method and apparatus for omnibus wiring of virtual mapping table entries Nov 8, 1998 Issued
Array ( [id] => 4281026 [patent_doc_number] => 06260129 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Management of fixed pages in memory for input/output operations' [patent_app_type] => 1 [patent_app_number] => 9/149052 [patent_app_country] => US [patent_app_date] => 1998-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5558 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/260/06260129.pdf [firstpage_image] =>[orig_patent_app_number] => 149052 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/149052
Management of fixed pages in memory for input/output operations Sep 7, 1998 Issued
Array ( [id] => 4370976 [patent_doc_number] => 06216198 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Cache memory accessible for continuous data without tag array indexing' [patent_app_type] => 1 [patent_app_number] => 9/148783 [patent_app_country] => US [patent_app_date] => 1998-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2409 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/216/06216198.pdf [firstpage_image] =>[orig_patent_app_number] => 148783 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/148783
Cache memory accessible for continuous data without tag array indexing Sep 3, 1998 Issued
Array ( [id] => 1549619 [patent_doc_number] => 06374341 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Apparatus and a method for variable size pages using fixed size translation lookaside buffer entries' [patent_app_type] => B1 [patent_app_number] => 09/146484 [patent_app_country] => US [patent_app_date] => 1998-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 7265 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/374/06374341.pdf [firstpage_image] =>[orig_patent_app_number] => 09146484 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/146484
Apparatus and a method for variable size pages using fixed size translation lookaside buffer entries Sep 1, 1998 Issued
Array ( [id] => 4400309 [patent_doc_number] => 06304949 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Data processor with localized memory reclamation' [patent_app_type] => 1 [patent_app_number] => 9/138780 [patent_app_country] => US [patent_app_date] => 1998-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4595 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/304/06304949.pdf [firstpage_image] =>[orig_patent_app_number] => 138780 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/138780
Data processor with localized memory reclamation Aug 23, 1998 Issued
Array ( [id] => 1513241 [patent_doc_number] => 06442647 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Method and apparatus for utilization of plural commands to improve read response times of data from a disk track' [patent_app_type] => B1 [patent_app_number] => 09/138813 [patent_app_country] => US [patent_app_date] => 1998-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2600 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/442/06442647.pdf [firstpage_image] =>[orig_patent_app_number] => 09138813 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/138813
Method and apparatus for utilization of plural commands to improve read response times of data from a disk track Aug 20, 1998 Issued
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