Search

Joseph D. Torres

Examiner (ID: 13957, Phone: (571)272-3829 , Office: P/2112 )

Most Active Art Unit
2112
Art Unit(s)
2112, 2133
Total Applications
2134
Issued Applications
1676
Pending Applications
96
Abandoned Applications
378

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18136599 [patent_doc_number] => 11562281 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-24 [patent_title] => Hierarchical portfolio optimization using clustering and near-term quantum computers [patent_app_type] => utility [patent_app_number] => 16/669700 [patent_app_country] => US [patent_app_date] => 2019-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12152 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16669700 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/669700
Hierarchical portfolio optimization using clustering and near-term quantum computers Oct 30, 2019 Issued
Array ( [id] => 18722137 [patent_doc_number] => 11799499 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-24 [patent_title] => Methods and apparatus for error-correcting difference-triangle-set product convolutional codes [patent_app_type] => utility [patent_app_number] => 17/287723 [patent_app_country] => US [patent_app_date] => 2019-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 18631 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17287723 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/287723
Methods and apparatus for error-correcting difference-triangle-set product convolutional codes Oct 21, 2019 Issued
Array ( [id] => 17003316 [patent_doc_number] => 11082147 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-03 [patent_title] => Processing method, device and system for overlap multiplexing system [patent_app_type] => utility [patent_app_number] => 16/659515 [patent_app_country] => US [patent_app_date] => 2019-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 12576 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16659515 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/659515
Processing method, device and system for overlap multiplexing system Oct 20, 2019 Issued
Array ( [id] => 16896970 [patent_doc_number] => 11038535 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-15 [patent_title] => Parity puncturing device for variable-length signaling information encoding, and parity puncturing method using same [patent_app_type] => utility [patent_app_number] => 16/658254 [patent_app_country] => US [patent_app_date] => 2019-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 9827 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16658254 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/658254
Parity puncturing device for variable-length signaling information encoding, and parity puncturing method using same Oct 20, 2019 Issued
Array ( [id] => 15505071 [patent_doc_number] => 20200052724 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => PARITY INTERLEAVING APPARATUS FOR ENCODING FIXED-LENGTH SIGNALING INFORMATION, AND PARITY INTERLEAVING METHOD USING SAME [patent_app_type] => utility [patent_app_number] => 16/658270 [patent_app_country] => US [patent_app_date] => 2019-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9506 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16658270 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/658270
Parity interleaving apparatus for encoding fixed-length signaling information, and parity interleaving method using same Oct 20, 2019 Issued
Array ( [id] => 15505257 [patent_doc_number] => 20200052817 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => METHODS AND APPARATUS FOR COMPACTLY DESCRIBING LIFTED LOW-DENSITY PARITY-CHECK (LDPC) CODES [patent_app_type] => utility [patent_app_number] => 16/655850 [patent_app_country] => US [patent_app_date] => 2019-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19463 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16655850 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/655850
Methods and apparatus for compactly describing lifted low-density parity-check (LDPC) codes Oct 16, 2019 Issued
Array ( [id] => 16690594 [patent_doc_number] => 20210073072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-11 [patent_title] => ERROR TOLERANT MEMORY ARRAY AND METHOD FOR PERFORMING ERROR CORRECTION IN A MEMORY ARRAY [patent_app_type] => utility [patent_app_number] => 16/588916 [patent_app_country] => US [patent_app_date] => 2019-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15560 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16588916 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/588916
Error tolerant memory array and method for performing error correction in a memory array Sep 29, 2019 Issued
Array ( [id] => 16928094 [patent_doc_number] => 11049583 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-29 [patent_title] => Semiconductor system with a training operation [patent_app_type] => utility [patent_app_number] => 16/587458 [patent_app_country] => US [patent_app_date] => 2019-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5686 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16587458 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/587458
Semiconductor system with a training operation Sep 29, 2019 Issued
Array ( [id] => 16729805 [patent_doc_number] => 20210096952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => METHOD AND SYSTEM FOR ERASURE CODED DATA PLACEMENT IN A LINKED NODE SYSTEM [patent_app_type] => utility [patent_app_number] => 16/587399 [patent_app_country] => US [patent_app_date] => 2019-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18038 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16587399 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/587399
Method and system for erasure coded data placement in a linked node system Sep 29, 2019 Issued
Array ( [id] => 15371091 [patent_doc_number] => 20200021310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-16 [patent_title] => INFORMATION PROCESSING METHOD AND APPARATUS, AND DEVICE [patent_app_type] => utility [patent_app_number] => 16/580398 [patent_app_country] => US [patent_app_date] => 2019-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15444 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16580398 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/580398
INFORMATION PROCESSING METHOD AND APPARATUS, AND DEVICE Sep 23, 2019 Abandoned
Array ( [id] => 17826483 [patent_doc_number] => 11431443 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-30 [patent_title] => HARQ codebook [patent_app_type] => utility [patent_app_number] => 16/580907 [patent_app_country] => US [patent_app_date] => 2019-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 13123 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16580907 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/580907
HARQ codebook Sep 23, 2019 Issued
Array ( [id] => 17390266 [patent_doc_number] => 20220038118 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-03 [patent_title] => Decoding Method and Device for Turbo product codes, decoder and computer storage medium [patent_app_type] => utility [patent_app_number] => 17/275730 [patent_app_country] => US [patent_app_date] => 2019-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13201 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17275730 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/275730
Decoding method and device for turbo product codes, decoder and computer storage medium Sep 11, 2019 Issued
Array ( [id] => 16737686 [patent_doc_number] => 10963338 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-30 [patent_title] => System and method for decoder assisted dynamic log-likelihood ratio (LLR) estimation for NAND flash memories [patent_app_type] => utility [patent_app_number] => 16/569619 [patent_app_country] => US [patent_app_date] => 2019-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10220 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16569619 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/569619
System and method for decoder assisted dynamic log-likelihood ratio (LLR) estimation for NAND flash memories Sep 11, 2019 Issued
Array ( [id] => 16802007 [patent_doc_number] => 10996951 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-04 [patent_title] => Plausibility-driven fault detection in string termination logic for fast exact substring match [patent_app_type] => utility [patent_app_number] => 16/567356 [patent_app_country] => US [patent_app_date] => 2019-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7937 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16567356 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/567356
Plausibility-driven fault detection in string termination logic for fast exact substring match Sep 10, 2019 Issued
Array ( [id] => 16746242 [patent_doc_number] => 10971242 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-06 [patent_title] => Sequential error capture during memory test [patent_app_type] => utility [patent_app_number] => 16/567508 [patent_app_country] => US [patent_app_date] => 2019-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3521 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16567508 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/567508
Sequential error capture during memory test Sep 10, 2019 Issued
Array ( [id] => 16691859 [patent_doc_number] => 20210074338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-11 [patent_title] => DEFECTIVE BIT LINE MANAGEMENT IN CONNECTION WITH A MEMORY ACCESS [patent_app_type] => utility [patent_app_number] => 16/562745 [patent_app_country] => US [patent_app_date] => 2019-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12894 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16562745 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/562745
Defective bit line management in connection with a memory access Sep 5, 2019 Issued
Array ( [id] => 17209502 [patent_doc_number] => 11169875 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-09 [patent_title] => Nonvolatile semiconductor memory device [patent_app_type] => utility [patent_app_number] => 16/561399 [patent_app_country] => US [patent_app_date] => 2019-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 28 [patent_no_of_words] => 21128 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16561399 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/561399
Nonvolatile semiconductor memory device Sep 4, 2019 Issued
Array ( [id] => 15301511 [patent_doc_number] => 20190393891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 16200 AND CODE RATE OF 3/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME [patent_app_type] => utility [patent_app_number] => 16/559329 [patent_app_country] => US [patent_app_date] => 2019-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5471 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16559329 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/559329
Low density parity check encoder having length of 16200 and code rate of 3/15, and low density parity check encoding method using the same Sep 2, 2019 Issued
Array ( [id] => 16767281 [patent_doc_number] => 10979073 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-13 [patent_title] => Low density parity check encoder having length of 64800 and code rate of 7/15, and low density parity check encoding method using the same [patent_app_type] => utility [patent_app_number] => 16/543349 [patent_app_country] => US [patent_app_date] => 2019-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 7061 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 1007 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16543349 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/543349
Low density parity check encoder having length of 64800 and code rate of 7/15, and low density parity check encoding method using the same Aug 15, 2019 Issued
Array ( [id] => 17530590 [patent_doc_number] => 11303299 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-12 [patent_title] => Transmitting apparatus and interleaving method thereof [patent_app_type] => utility [patent_app_number] => 16/541890 [patent_app_country] => US [patent_app_date] => 2019-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 45 [patent_no_of_words] => 45991 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16541890 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/541890
Transmitting apparatus and interleaving method thereof Aug 14, 2019 Issued
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