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Joseph D. Torres

Examiner (ID: 4604)

Most Active Art Unit
2112
Art Unit(s)
2133, 2112
Total Applications
2105
Issued Applications
1653
Pending Applications
105
Abandoned Applications
371

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19829211 [patent_doc_number] => 12250008 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-11 [patent_title] => System and method for serialized communication [patent_app_type] => utility [patent_app_number] => 18/143288 [patent_app_country] => US [patent_app_date] => 2023-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3632 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18143288 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/143288
System and method for serialized communication May 3, 2023 Issued
Array ( [id] => 18866738 [patent_doc_number] => 20230421175 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => METHOD AND APPARATUS FOR DECODING LOW-DENSITY PARITY-CHECK (LDPC) CODE [patent_app_type] => utility [patent_app_number] => 18/143343 [patent_app_country] => US [patent_app_date] => 2023-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7376 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 392 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18143343 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/143343
Method and apparatus for decoding low-density parity-check (LDPC) code May 3, 2023 Issued
Array ( [id] => 19016924 [patent_doc_number] => 11923872 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-05 [patent_title] => Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 7/15 and quadrature phase shift keying, and bit interleaving method using same [patent_app_type] => utility [patent_app_number] => 18/309278 [patent_app_country] => US [patent_app_date] => 2023-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6856 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 1339 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18309278 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/309278
Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 7/15 and quadrature phase shift keying, and bit interleaving method using same Apr 27, 2023 Issued
Array ( [id] => 19516581 [patent_doc_number] => 20240348267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => DEVICES, SYSTEMS, AND METHODS FOR ENCODING AND DECODING CODEWORDS [patent_app_type] => utility [patent_app_number] => 18/134690 [patent_app_country] => US [patent_app_date] => 2023-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10402 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18134690 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/134690
Devices, systems, and methods for encoding and decoding codewords Apr 13, 2023 Issued
Array ( [id] => 20223720 [patent_doc_number] => 20250286651 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-11 [patent_title] => Multi-Layer Forward Error Correction (FEC) for Jamming Resiliency [patent_app_type] => utility [patent_app_number] => 18/131203 [patent_app_country] => US [patent_app_date] => 2023-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18131203 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/131203
Multi-layer forward error correction (FEC) for jamming resiliency Apr 4, 2023 Issued
Array ( [id] => 18614762 [patent_doc_number] => 20230281499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => SCALABLE PHOTONIC QUANTUM COMPUTING WITH HYBRID RESOURCE STATES [patent_app_type] => utility [patent_app_number] => 18/126807 [patent_app_country] => US [patent_app_date] => 2023-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14857 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18126807 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/126807
SCALABLE PHOTONIC QUANTUM COMPUTING WITH HYBRID RESOURCE STATES Mar 26, 2023 Pending
Array ( [id] => 18614762 [patent_doc_number] => 20230281499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => SCALABLE PHOTONIC QUANTUM COMPUTING WITH HYBRID RESOURCE STATES [patent_app_type] => utility [patent_app_number] => 18/126807 [patent_app_country] => US [patent_app_date] => 2023-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14857 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18126807 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/126807
SCALABLE PHOTONIC QUANTUM COMPUTING WITH HYBRID RESOURCE STATES Mar 26, 2023 Pending
Array ( [id] => 19766464 [patent_doc_number] => 12224772 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => Compression/decompression apparatus, storage system, and compression/decompression method [patent_app_type] => utility [patent_app_number] => 18/125188 [patent_app_country] => US [patent_app_date] => 2023-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7162 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 406 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18125188 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/125188
Compression/decompression apparatus, storage system, and compression/decompression method Mar 22, 2023 Issued
Array ( [id] => 20265850 [patent_doc_number] => 12436842 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Systems and methods of distributed parity calculation offloading [patent_app_type] => utility [patent_app_number] => 18/123238 [patent_app_country] => US [patent_app_date] => 2023-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 2074 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18123238 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/123238
Systems and methods of distributed parity calculation offloading Mar 16, 2023 Issued
Array ( [id] => 20265850 [patent_doc_number] => 12436842 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Systems and methods of distributed parity calculation offloading [patent_app_type] => utility [patent_app_number] => 18/123238 [patent_app_country] => US [patent_app_date] => 2023-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 2074 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18123238 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/123238
Systems and methods of distributed parity calculation offloading Mar 16, 2023 Issued
Array ( [id] => 19654244 [patent_doc_number] => 12176044 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-12-24 [patent_title] => Bit error rate estimation and classification in NAND flash memory [patent_app_type] => utility [patent_app_number] => 18/123232 [patent_app_country] => US [patent_app_date] => 2023-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 14162 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18123232 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/123232
Bit error rate estimation and classification in NAND flash memory Mar 16, 2023 Issued
Array ( [id] => 18474159 [patent_doc_number] => 20230208447 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => CONCATENATED ERROR CORRECTING CODES [patent_app_type] => utility [patent_app_number] => 18/177207 [patent_app_country] => US [patent_app_date] => 2023-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4722 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18177207 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/177207
Concatenated error correcting codes Mar 1, 2023 Issued
Array ( [id] => 19874334 [patent_doc_number] => 12267210 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-01 [patent_title] => Adapting forward error correction (FEC) or link parameters for improved post-FEC performance [patent_app_type] => utility [patent_app_number] => 18/112406 [patent_app_country] => US [patent_app_date] => 2023-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 14047 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18112406 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/112406
Adapting forward error correction (FEC) or link parameters for improved post-FEC performance Feb 20, 2023 Issued
Array ( [id] => 18883761 [patent_doc_number] => 20240007130 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => CHANNEL CODING METHOD, PROCESSING DEVICE, COMMUNICATION METHOD AND DEVICE [patent_app_type] => utility [patent_app_number] => 18/170725 [patent_app_country] => US [patent_app_date] => 2023-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16807 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18170725 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/170725
Channel coding method, processing device, communication method and device Feb 16, 2023 Issued
Array ( [id] => 19962814 [patent_doc_number] => 12332310 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-17 [patent_title] => Built-in testing in modular system-on-chip device [patent_app_type] => utility [patent_app_number] => 18/170467 [patent_app_country] => US [patent_app_date] => 2023-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1157 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18170467 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/170467
Built-in testing in modular system-on-chip device Feb 15, 2023 Issued
Array ( [id] => 19399524 [patent_doc_number] => 12073910 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-27 [patent_title] => Semiconductor memory devices [patent_app_type] => utility [patent_app_number] => 18/169769 [patent_app_country] => US [patent_app_date] => 2023-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 31 [patent_no_of_words] => 13774 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18169769 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/169769
Semiconductor memory devices Feb 14, 2023 Issued
Array ( [id] => 19099582 [patent_doc_number] => 20240118810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-11 [patent_title] => MEMORY SYSTEM AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/107510 [patent_app_country] => US [patent_app_date] => 2023-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9607 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18107510 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/107510
MEMORY SYSTEM AND OPERATING METHOD THEREOF Feb 8, 2023 Pending
Array ( [id] => 20029588 [patent_doc_number] => 20250167810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-22 [patent_title] => HIGH-PERFORMANCE SCL BIT-FLIP DECODER FOR CONCATENATED POLAR CODES [patent_app_type] => utility [patent_app_number] => 18/839563 [patent_app_country] => US [patent_app_date] => 2023-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2514 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18839563 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/839563
HIGH-PERFORMANCE SCL BIT-FLIP DECODER FOR CONCATENATED POLAR CODES Jan 31, 2023 Pending
Array ( [id] => 19537779 [patent_doc_number] => 12130330 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-29 [patent_title] => Integrated circuit including constant-0 flip flops reconfigured to provide observable and controllable test points [patent_app_type] => utility [patent_app_number] => 18/159486 [patent_app_country] => US [patent_app_date] => 2023-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5665 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18159486 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/159486
Integrated circuit including constant-0 flip flops reconfigured to provide observable and controllable test points Jan 24, 2023 Issued
Array ( [id] => 19610800 [patent_doc_number] => 12159680 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-03 [patent_title] => Data writing method, test method, writing apparatus, medium, and electronic device [patent_app_type] => utility [patent_app_number] => 18/154924 [patent_app_country] => US [patent_app_date] => 2023-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6679 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18154924 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/154924
Data writing method, test method, writing apparatus, medium, and electronic device Jan 15, 2023 Issued
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